MG32F10x Standard Peripherals Firmware Library

mg32f10x_dmac.h
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10 /* Define to prevent recursive inclusion -------------------------------------*/
11 #ifndef __MG32F10x_DMAC_H
12 #define __MG32F10x_DMAC_H
13
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17
18 /* Includes ------------------------------------------------------------------*/
19 #include "mg32f10x.h"
20
29 /* Exported types ------------------------------------------------------------*/
30
34 typedef struct
35 {
36 FunctionalState DMAC_SourceGather;
37 uint32_t DMAC_SourceGatherCount;
38 uint32_t DMAC_SourceGatherInterval;
39 } DMAC_SourceGatherInitTypeDef;
40
44 typedef struct
45 {
46 FunctionalState DMAC_DestinationScatter;
47 uint32_t DMAC_DestinationScatterCount;
48 uint32_t DMAC_DestinationScatterInterval;
49 } DMAC_DestinationScatterInitTypeDef;
50
54 typedef struct
55 {
56 uint32_t DMAC_SourceBaseAddr;
58 uint32_t DMAC_DestinationBaseAddr;
60 uint32_t DMAC_Interrupt;
63 uint32_t DMAC_SourceTransferWidth;
66 uint32_t DMAC_DestinationTransferWidth;
69 uint32_t DMAC_SourceAddrInc;
72 uint32_t DMAC_DestinationAddrInc;
75 uint32_t DMAC_SourceTransactionLength;
79 uint32_t DMAC_DestinationTransactionLength;
83 uint32_t DMAC_TransferTypeAndFlowControl;
86 uint32_t DMAC_SourceMasterInterface;
89 uint32_t DMAC_DestinationMasterInterface;
92 uint32_t DMAC_BlockTransferSize;
96 uint32_t DMAC_SourceHandshakingInterfaceSelect;
100 uint32_t DMAC_DestinationHandshakingInterfaceSelect;
104 uint32_t DMAC_SourceHandshakingInterfacePolarity;
107 uint32_t DMAC_DestinationHandshakingInterfacePolarity;
110 uint32_t DMAC_AutomaticSourceReload;
114 uint32_t DMAC_AutomaticDestinationReload;
118 uint32_t DMAC_FlowControlMode;
121 uint32_t DMAC_FIFOMode;
124 uint8_t DMAC_ChannelPriority;
128 uint8_t DMAC_ProtectionControl;
133 uint8_t DMAC_SourceHardwareHandshakingInterfaceAssign;
137 uint8_t DMAC_DestinationHardwareHandshakingInterfaceAssign;
141 uint16_t DMAC_MaximumAMBABurstLength;
145 } DMAC_Channel_InitTypeDef;
146
147 /* Exported constants --------------------------------------------------------*/
148
156 #define DMAC_Interrupt_Enable ((uint32_t)0x00000001)
157 #define DMAC_Interrupt_Disable ((uint32_t)0x00000000)
158
166 #define DMAC_SourceTransferWidth_8b DMAC_CTLL_SRC_TR_WIDTH_8
167 #define DMAC_SourceTransferWidth_16b DMAC_CTLL_SRC_TR_WIDTH_16
168 #define DMAC_SourceTransferWidth_32b DMAC_CTLL_SRC_TR_WIDTH_32
169
177 #define DMAC_DestinationTransferWidth_8b DMAC_CTLL_DST_TR_WIDTH_8
178 #define DMAC_DestinationTransferWidth_16b DMAC_CTLL_DST_TR_WIDTH_16
179 #define DMAC_DestinationTransferWidth_32b DMAC_CTLL_DST_TR_WIDTH_32
180
188 #define DMAC_SourceAddrInc_Increment DMAC_CTLL_SINC_INC
189 #define DMAC_SourceAddrInc_Decrement DMAC_CTLL_SINC_DEC
190 #define DMAC_SourceAddrInc_NoChange DMAC_CTLL_SINC_NO
191
199 #define DMAC_DestinationAddrInc_Increment DMAC_CTLL_DINC_INC
200 #define DMAC_DestinationAddrInc_Decrement DMAC_CTLL_DINC_DEC
201 #define DMAC_DestinationAddrInc_NoChange DMAC_CTLL_DINC_NO
202
210 #define DMAC_SourceTransactionLength_1 DMAC_CTLL_SRC_MSIZE_1
211 #define DMAC_SourceTransactionLength_4 DMAC_CTLL_SRC_MSIZE_4
212 #define DMAC_SourceTransactionLength_8 DMAC_CTLL_SRC_MSIZE_8
213
221 #define DMAC_DestinationTransactionLength_1 DMAC_CTLL_DEST_MSIZE_1
222 #define DMAC_DestinationTransactionLength_4 DMAC_CTLL_DEST_MSIZE_4
223 #define DMAC_DestinationTransactionLength_8 DMAC_CTLL_DEST_MSIZE_8
224
232 #define DMAC_TransferTypeAndFlowControl_MemoryToMemory_DMAC DMAC_CTLL_TT_FC_M2M_DMAC
233 #define DMAC_TransferTypeAndFlowControl_MemoryToPeripheral_DMAC DMAC_CTLL_TT_FC_M2P_DMAC
234 #define DMAC_TransferTypeAndFlowControl_PeripheralToMemory_DMAC DMAC_CTLL_TT_FC_P2M_DMAC
235 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_DMAC DMAC_CTLL_TT_FC_P2P_DMAC
236 /* The following definitions is only used for DMACx channel0. */
237 #define DMAC_TransferTypeAndFlowControl_PeripheralToMemory_Peripheral DMAC_CTLL_TT_FC_P2M_PERIPH
238 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_SourcePeripheral DMAC_CTLL_TT_FC_P2P_SRC_PERIPH
239 #define DMAC_TransferTypeAndFlowControl_MemoryToPeripheral_Peripheral DMAC_CTLL_TT_FC_M2P_PERIPH
240 #define DMAC_TransferTypeAndFlowControl_PeripheralToPeripheral_DestinationPeripheral DMAC_CTLL_TT_FC_P2P_DST_PERIPH
241
249 #define DMAC_SourceMasterInterface_APB (0x0U << 25)
250 #define DMAC_SourceMasterInterface_AHB (0x1U << 25)
251
259 #define DMAC_DestinationMasterInterface_APB (0x0U << 23)
260 #define DMAC_DestinationMasterInterface_AHB (0x1U << 23)
261
269 #define DMAC_SourceHandshakingInterfaceSelect_Hardware (0x0U << 11)
270 #define DMAC_SourceHandshakingInterfaceSelect_Software (0x1U << 11)
271
279 #define DMAC_DestinationHandshakingInterfaceSelect_Hardware (0x0U << 10)
280 #define DMAC_DestinationHandshakingInterfaceSelect_Software (0x1U << 10)
281
289 #define DMAC_SourceHandshakingInterfacePolarity_High (0x0U << 19)
290 #define DMAC_SourceHandshakingInterfacePolarity_Low (0x1U << 19)
291
299 #define DMAC_DestinationHandshakingInterfacePolarity_High (0x0U << 18)
300 #define DMAC_DestinationHandshakingInterfacePolarity_Low (0x1U << 18)
301
309 #define DMAC_AutomaticSourceReload_Enable (DMAC_CFGL_RELOAD_SRC)
310 #define DMAC_AutomaticSourceReload_Disable ((uint32_t)0x00000000)
311
319 #define DMAC_AutomaticDestinationReload_Enable (DMAC_CFGL_RELOAD_DST)
320 #define DMAC_AutomaticDestinationReload_Disable ((uint32_t)0x00000000)
321
329 #define DMAC_FlowControlMode_0 (0x0 << 0)
330 #define DMAC_FlowControlMode_1 (0x1 << 0)
331
339 #define DMAC_FIFOMode_0 (0x0 << 1)
340 #define DMAC_FIFOMode_1 (0x1 << 1)
341
349 /* The following definitions is only used for DMAC1. */
350 #define DMAC_HardwareHandshakingInterface_TIM1_CH1__TIM2_UP__TIM3_CH3 0
351 #define DMAC_HardwareHandshakingInterface_TIM1_CH4__TIM1_TRIG__TIM1_COM__TIM4_CH2 1
352 #define DMAC_HardwareHandshakingInterface_TIM1_UP__TIM2_CH1__TIM4_CH3 2
353 #define DMAC_HardwareHandshakingInterface_TIM1_CH3__TIM3_CH1__TIM3_TRIG 3
354 #define DMAC_HardwareHandshakingInterface_TIM2_CH3__TIM4_CH1 4
355 #define DMAC_HardwareHandshakingInterface_TIM2_CH2__TIM2_CH4__TIM4_UP 5
356 #define DMAC_HardwareHandshakingInterface_TIM3_CH4__TIM3_UP__TIM1_CH2 6
357 #define DMAC_HardwareHandshakingInterface_QSPI_RX 7
358 #define DMAC_HardwareHandshakingInterface_QSPI_TX 8
359 #define DMAC_HardwareHandshakingInterface_SPIS1_RX 9
360 #define DMAC_HardwareHandshakingInterface_SPIS1_TX 10
361 #define DMAC_HardwareHandshakingInterface_UART1_RX 11
362 #define DMAC_HardwareHandshakingInterface_UART1_TX 12
363 #define DMAC_HardwareHandshakingInterface_ADC_Regular 13
364 #define DMAC_HardwareHandshakingInterface_ADC_Injected 14
365
366 /* The following definitions is only used for DMAC2. */
367 #define DMAC_HardwareHandshakingInterface_SPIM2_RX 0
368 #define DMAC_HardwareHandshakingInterface_SPIM2_TX 1
369 #define DMAC_HardwareHandshakingInterface_SPIS2_RX 2
370 #define DMAC_HardwareHandshakingInterface_SPIS2_TX 3
371 #define DMAC_HardwareHandshakingInterface_UART2_RX 4
372 #define DMAC_HardwareHandshakingInterface_UART2_TX 5
373 #define DMAC_HardwareHandshakingInterface_UART3_RX 6
374 #define DMAC_HardwareHandshakingInterface_UART3_TX 7
375 #define DMAC_HardwareHandshakingInterface_I2C1_RX 8
376 #define DMAC_HardwareHandshakingInterface_I2C1_TX 9
377 #define DMAC_HardwareHandshakingInterface_I2C2_RX 10
378 #define DMAC_HardwareHandshakingInterface_I2C2_TX 11
379
387 #define DMAC_Channel_0 ((uint8_t)0x00)
388 #define DMAC_Channel_1 ((uint8_t)0x01)
389 #define DMAC_Channel_2 ((uint8_t)0x02)
390
398 #define DMAC_IT_TFR ((uint16_t)0x0000) /* Transfer complete interrupt */
399 #define DMAC_IT_BLOCK ((uint16_t)0x0008) /* Block complete interrupt */
400 #define DMAC_IT_SRCTRAN ((uint16_t)0x0010) /* Source transaction complete interrupt */
401 #define DMAC_IT_DSTTRAN ((uint16_t)0x0018) /* Destination transaction complete interrupt */
402 #define DMAC_IT_ERR ((uint16_t)0x0020) /* Error interrupt */
403
411 /* Exported macro ------------------------------------------------------------*/
412 /* Exported functions --------------------------------------------------------*/
413
414 void DMAC_DeInit(DMAC_TypeDef* DMACx);
415 void DMAC_Channel_Init(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, DMAC_Channel_InitTypeDef* DMAC_Channel_InitStruct);
416 void DMAC_Channel_StructInit(DMAC_Channel_InitTypeDef* DMAC_Channel_InitStruct);
417 void DMAC_Channel_SourceGatherConfig(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, DMAC_SourceGatherInitTypeDef* DMAC_SourceGatherInitStruct);
418 void DMAC_Channel_DestinationScatterConfig(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, DMAC_DestinationScatterInitTypeDef* DMAC_DestinationScatterInitStruct);
419 void DMAC_Channel_SetSourceAddress(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint32_t SourceAddress);
420 void DMAC_Channel_SetDestinationAddress(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint32_t DestinationAddress);
421 void DMAC_Channel_SetBlockTransferSize(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint16_t DMAC_BlockTransferSize);
422 uint16_t DMAC_Channel_GetBlockTransferSize(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
423 void DMAC_Channel_SuspendCmd(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, FunctionalState NewState);
424 FlagStatus DMAC_Channel_IsFIFOEmpty(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
425
426 /* Configuration and Channel Enable functions *********************************/
427 void DMAC_Cmd(DMAC_TypeDef* DMACx, FunctionalState NewState);
428 FunctionalState DMAC_GetCmdStatus(DMAC_TypeDef* DMACx);
429 void DMAC_ChannelCmd(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, FunctionalState NewState);
430 FunctionalState DMAC_GetChannelCmdStatus(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
431
432 /* Interrupts management functions ********************************************/
433 void DMAC_ITConfig(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT, FunctionalState NewState);
434 ITStatus DMAC_GetRawITStatus(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT);
435 ITStatus DMAC_GetITStatus(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT);
436 ITStatus DMAC_GetCombinedITStatus(DMAC_TypeDef* DMACx, uint16_t DMAC_IT);
437 void DMAC_ClearITPendingBit(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT);
438
439 /* Software Handshaking interface management functions ************************/
440 void DMAC_SWHS_SetReqSrcSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, SignalState NewState);
441 void DMAC_SWHS_SetReqDstSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, SignalState NewState);
442 void DMAC_SWHS_SetSglReqSrcSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, SignalState NewState);
443 void DMAC_SWHS_SetSglReqDstSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, SignalState NewState);
444 void DMAC_SWHS_SetLstSrcSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, SignalState NewState);
445 void DMAC_SWHS_SetLstDstSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel, SignalState NewState);
446 SignalState DMAC_SWHS_GetReqSrcSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
447 SignalState DMAC_SWHS_GetReqDstSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
448 SignalState DMAC_SWHS_GetSglReqSrcSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
449 SignalState DMAC_SWHS_GetSglReqDstSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
450 SignalState DMAC_SWHS_GetLstSrcSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
451 SignalState DMAC_SWHS_GetLstDstSignalState(DMAC_TypeDef* DMACx, uint8_t DMAC_Channel);
452
461 #ifdef __cplusplus
462 }
463 #endif
464
465 #endif /* __MG32F10x_DMAC_H */
DMAC_SWHS_GetLstDstSignalState
SignalState DMAC_SWHS_GetLstDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of LstDst signal for the corresponding channel.
Definition: mg32f10x_dmac.c:910
DMAC_Channel_InitTypeDef::DMAC_ProtectionControl
uint8_t DMAC_ProtectionControl
Definition: mg32f10x_dmac.h:128
DMAC_SWHS_GetSglReqDstSignalState
SignalState DMAC_SWHS_GetSglReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of SglReqDst signal for the corresponding channel.
Definition: mg32f10x_dmac.c:854
DMAC_DestinationScatterInitTypeDef
DMAC Destination Scatter Structure definition
Definition: mg32f10x_dmac.h:44
DMAC_Channel_InitTypeDef::DMAC_FIFOMode
uint32_t DMAC_FIFOMode
Definition: mg32f10x_dmac.h:121
DMAC_Channel_InitTypeDef::DMAC_DestinationHandshakingInterfaceSelect
uint32_t DMAC_DestinationHandshakingInterfaceSelect
Definition: mg32f10x_dmac.h:100
DMAC_ChannelCmd
void DMAC_ChannelCmd(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, FunctionalState NewState)
Enables or disables the specified DMACx Channely.
Definition: mg32f10x_dmac.c:391
DMAC_Channel_InitTypeDef::DMAC_Interrupt
uint32_t DMAC_Interrupt
Definition: mg32f10x_dmac.h:60
DMAC_Channel_InitTypeDef
DMAC Channel Init Structure definition
Definition: mg32f10x_dmac.h:54
DMAC_SourceGatherInitTypeDef
DMAC Source Gather Structure definition
Definition: mg32f10x_dmac.h:34
DMAC_SWHS_SetReqDstSignalState
void DMAC_SWHS_SetReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of ReqDst signal for the corresponding channels.
Definition: mg32f10x_dmac.c:640
DMAC_DeInit
void DMAC_DeInit(DMAC_TypeDef *DMACx)
Deinitializes the DMACx peripheral registers to their default reset values.
Definition: mg32f10x_dmac.c:40
DMAC_Channel_InitTypeDef::DMAC_SourceHandshakingInterfacePolarity
uint32_t DMAC_SourceHandshakingInterfacePolarity
Definition: mg32f10x_dmac.h:104
DMAC_Channel_InitTypeDef::DMAC_SourceAddrInc
uint32_t DMAC_SourceAddrInc
Definition: mg32f10x_dmac.h:69
DMAC_Channel_InitTypeDef::DMAC_ChannelPriority
uint8_t DMAC_ChannelPriority
Definition: mg32f10x_dmac.h:124
DMAC_Channel_InitTypeDef::DMAC_DestinationAddrInc
uint32_t DMAC_DestinationAddrInc
Definition: mg32f10x_dmac.h:72
DMAC_Channel_StructInit
void DMAC_Channel_StructInit(DMAC_Channel_InitTypeDef *DMAC_Channel_InitStruct)
Fills each DMAC_Channel_InitStruct member with its default value.
Definition: mg32f10x_dmac.c:109
DMAC_Channel_InitTypeDef::DMAC_SourceBaseAddr
uint32_t DMAC_SourceBaseAddr
Definition: mg32f10x_dmac.h:56
DMAC_SWHS_SetReqSrcSignalState
void DMAC_SWHS_SetReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of ReqSrc signal for the corresponding channels.
Definition: mg32f10x_dmac.c:614
DMAC_Channel_SourceGatherConfig
void DMAC_Channel_SourceGatherConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_SourceGatherInitTypeDef *DMAC_SourceGatherInitStruct)
Initializes the source gather of DMACx Channely.
Definition: mg32f10x_dmac.c:165
DMAC_Cmd
void DMAC_Cmd(DMAC_TypeDef *DMACx, FunctionalState NewState)
Enables or disables the specified DMACx peripheral.
Definition: mg32f10x_dmac.c:345
DMAC_Channel_InitTypeDef::DMAC_DestinationHardwareHandshakingInterfaceAssign
uint8_t DMAC_DestinationHardwareHandshakingInterfaceAssign
Definition: mg32f10x_dmac.h:137
DMAC_GetITStatus
ITStatus DMAC_GetITStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Checks whether the specified DMACx Channely interrupt has occurred or not.
Definition: mg32f10x_dmac.c:524
DMAC_Channel_InitTypeDef::DMAC_MaximumAMBABurstLength
uint16_t DMAC_MaximumAMBABurstLength
Definition: mg32f10x_dmac.h:141
DMAC_Channel_SuspendCmd
void DMAC_Channel_SuspendCmd(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, FunctionalState NewState)
Forces or releases the current DMACx Channely transfer suspend.
Definition: mg32f10x_dmac.c:295
DMAC_ITConfig
void DMAC_ITConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT, FunctionalState NewState)
Enables or disables the specified DMACx Channely interrupts.
Definition: mg32f10x_dmac.c:452
DMAC_ClearITPendingBit
void DMAC_ClearITPendingBit(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Clears the DMACx's interrupt pending bits.
Definition: mg32f10x_dmac.c:590
DMAC_Channel_GetBlockTransferSize
uint16_t DMAC_Channel_GetBlockTransferSize(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the number of remaining data units in the current DMACx Channely block transfer.
Definition: mg32f10x_dmac.c:276
DMAC_Channel_InitTypeDef::DMAC_SourceHardwareHandshakingInterfaceAssign
uint8_t DMAC_SourceHardwareHandshakingInterfaceAssign
Definition: mg32f10x_dmac.h:133
DMAC_SWHS_SetSglReqSrcSignalState
void DMAC_SWHS_SetSglReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of SglReqSrc signal for the corresponding channels.
Definition: mg32f10x_dmac.c:666
DMAC_Channel_InitTypeDef::DMAC_AutomaticSourceReload
uint32_t DMAC_AutomaticSourceReload
Definition: mg32f10x_dmac.h:110
DMAC_TypeDef
Definition: mg32f10x.h:521
DMAC_Channel_InitTypeDef::DMAC_AutomaticDestinationReload
uint32_t DMAC_AutomaticDestinationReload
Definition: mg32f10x_dmac.h:114
DMAC_SWHS_GetSglReqSrcSignalState
SignalState DMAC_SWHS_GetSglReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of SglReqSrc signal for the corresponding channel.
Definition: mg32f10x_dmac.c:826
DMAC_Channel_InitTypeDef::DMAC_DestinationHandshakingInterfacePolarity
uint32_t DMAC_DestinationHandshakingInterfacePolarity
Definition: mg32f10x_dmac.h:107
DMAC_Channel_SetDestinationAddress
void DMAC_Channel_SetDestinationAddress(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint32_t DestinationAddress)
Sets the destination address of the specified DMACx Channely.
Definition: mg32f10x_dmac.c:240
DMAC_Channel_Init
void DMAC_Channel_Init(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_Channel_InitTypeDef *DMAC_Channel_InitStruct)
Initializes the DMACx Channely according to the specified parameters in the DMAC_Channel_InitStruct s...
Definition: mg32f10x_dmac.c:69
DMAC_Channel_IsFIFOEmpty
FlagStatus DMAC_Channel_IsFIFOEmpty(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Checks whether the DMACx Channely FIFO is empty or not.
Definition: mg32f10x_dmac.c:317
DMAC_Channel_SetSourceAddress
void DMAC_Channel_SetSourceAddress(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint32_t SourceAddress)
Sets the source address of the specified DMACx Channely.
Definition: mg32f10x_dmac.c:222
DMAC_SWHS_GetLstSrcSignalState
SignalState DMAC_SWHS_GetLstSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of LstSrc signal for the corresponding channel.
Definition: mg32f10x_dmac.c:882
DMAC_GetCmdStatus
FunctionalState DMAC_GetCmdStatus(DMAC_TypeDef *DMACx)
Returns the status of EN bit for the specified DMACx.
Definition: mg32f10x_dmac.c:362
DMAC_GetCombinedITStatus
ITStatus DMAC_GetCombinedITStatus(DMAC_TypeDef *DMACx, uint16_t DMAC_IT)
Checks whether the specified DMACx interrupt has occurred or not.
Definition: mg32f10x_dmac.c:555
DMAC_SWHS_SetLstDstSignalState
void DMAC_SWHS_SetLstDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of LstDst signal for the corresponding channels.
Definition: mg32f10x_dmac.c:744
DMAC_GetChannelCmdStatus
FunctionalState DMAC_GetChannelCmdStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the status of EN bit for the specified DMACx Channely.
Definition: mg32f10x_dmac.c:415
DMAC_Channel_InitTypeDef::DMAC_SourceTransactionLength
uint32_t DMAC_SourceTransactionLength
Definition: mg32f10x_dmac.h:75
DMAC_Channel_SetBlockTransferSize
void DMAC_Channel_SetBlockTransferSize(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_BlockTransferSize)
Sets the number of data units to be transferred on the block transfer.
Definition: mg32f10x_dmac.c:259
DMAC_Channel_InitTypeDef::DMAC_BlockTransferSize
uint32_t DMAC_BlockTransferSize
Definition: mg32f10x_dmac.h:92
DMAC_Channel_DestinationScatterConfig
void DMAC_Channel_DestinationScatterConfig(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, DMAC_DestinationScatterInitTypeDef *DMAC_DestinationScatterInitStruct)
Initializes the destination scatter of DMACx Channely.
Definition: mg32f10x_dmac.c:194
DMAC_SWHS_GetReqDstSignalState
SignalState DMAC_SWHS_GetReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of ReqDst signal for the corresponding channel.
Definition: mg32f10x_dmac.c:798
DMAC_Channel_InitTypeDef::DMAC_TransferTypeAndFlowControl
uint32_t DMAC_TransferTypeAndFlowControl
Definition: mg32f10x_dmac.h:83
DMAC_Channel_InitTypeDef::DMAC_DestinationTransferWidth
uint32_t DMAC_DestinationTransferWidth
Definition: mg32f10x_dmac.h:66
DMAC_SWHS_SetSglReqDstSignalState
void DMAC_SWHS_SetSglReqDstSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of SglReqDst signal for the corresponding channels.
Definition: mg32f10x_dmac.c:692
DMAC_SWHS_GetReqSrcSignalState
SignalState DMAC_SWHS_GetReqSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel)
Returns the state of ReqSrc signal for the corresponding channel.
Definition: mg32f10x_dmac.c:770
DMAC_Channel_InitTypeDef::DMAC_DestinationTransactionLength
uint32_t DMAC_DestinationTransactionLength
Definition: mg32f10x_dmac.h:79
DMAC_Channel_InitTypeDef::DMAC_DestinationMasterInterface
uint32_t DMAC_DestinationMasterInterface
Definition: mg32f10x_dmac.h:89
DMAC_Channel_InitTypeDef::DMAC_SourceHandshakingInterfaceSelect
uint32_t DMAC_SourceHandshakingInterfaceSelect
Definition: mg32f10x_dmac.h:96
DMAC_SWHS_SetLstSrcSignalState
void DMAC_SWHS_SetLstSrcSignalState(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, SignalState NewState)
Controls the state of LstSrc signal for the corresponding channels.
Definition: mg32f10x_dmac.c:718
DMAC_Channel_InitTypeDef::DMAC_SourceTransferWidth
uint32_t DMAC_SourceTransferWidth
Definition: mg32f10x_dmac.h:63
DMAC_Channel_InitTypeDef::DMAC_DestinationBaseAddr
uint32_t DMAC_DestinationBaseAddr
Definition: mg32f10x_dmac.h:58
DMAC_GetRawITStatus
ITStatus DMAC_GetRawITStatus(DMAC_TypeDef *DMACx, uint8_t DMAC_Channel, uint16_t DMAC_IT)
Checks whether the specified DMACx Channely raw interrupt status.
Definition: mg32f10x_dmac.c:488
DMAC_Channel_InitTypeDef::DMAC_SourceMasterInterface
uint32_t DMAC_SourceMasterInterface
Definition: mg32f10x_dmac.h:86
DMAC_Channel_InitTypeDef::DMAC_FlowControlMode
uint32_t DMAC_FlowControlMode
Definition: mg32f10x_dmac.h:118