MG32F10x Standard Peripherals Firmware Library

成员变量
DMAC_TypeDef结构体 参考
CMSIS » Mg32f10x

## 成员变量
struct {
__IOM uint32_t SAR
uint32_t Undefined_SAR
__IOM uint32_t DAR
uint32_t Undefined_DAR
uint32_t RESERVED0 [2]
__IOM uint32_t CTLL
__IOM uint32_t CTLH
uint32_t RESERVED1 [8]
__IOM uint32_t CFGL
__IOM uint32_t CFGH
__IOM uint32_t SGR
uint32_t Undefined_SGR
__IOM uint32_t DSR
uint32_t Undefined_DSR
} | Ch [3]
uint32_t | RESERVED2 [110]
__IM uint32_t | RawTfr
uint32_t | Undefined_RawTfr
__IM uint32_t | RawBlock
uint32_t | Undefined_RawBlock
__IM uint32_t | RawSrcTran
uint32_t | Undefined_RawSrcTran
__IM uint32_t | RawDstTran
uint32_t | Undefined_RawDstTran
__IM uint32_t | RawErr
uint32_t | Undefined_RawErr
__IM uint32_t | StatusTfr
uint32_t | Undefined_StatusTfr
__IM uint32_t | StatusBlock
uint32_t | Undefined_StatusBlock
__IM uint32_t | StatusSrcTran
uint32_t | Undefined_StatusSrcTran
__IM uint32_t | StatusDstTran
uint32_t | Undefined_StatusDstTran
__IM uint32_t | StatusErr
uint32_t | Undefined_StatusErr
__IOM uint32_t | MaskTfr
uint32_t | Undefined_MaskTfr
__IOM uint32_t | MaskBlock
uint32_t | Undefined_MaskBlock
__IOM uint32_t | MaskSrcTran
uint32_t | Undefined_MaskSrcTran
__IOM uint32_t | MaskDstTran
uint32_t | Undefined_MaskDstTran
__IOM uint32_t | MaskErr
uint32_t | Undefined_MaskErr
__OM uint32_t | ClearTfr
uint32_t | Undefined_ClearTfr
__OM uint32_t | ClearBlock
uint32_t | Undefined_ClearBlock
__OM uint32_t | ClearSrcTran
uint32_t | Undefined_ClearSrcTran
__OM uint32_t | ClearDstTran
uint32_t | Undefined_ClearDstTran
__OM uint32_t | ClearErr
uint32_t | Undefined_ClearErr
__IM uint32_t | StatusInt
uint32_t | Undefined_StatusInt
__IOM uint32_t | ReqSrcReg
uint32_t | Undefined_ReqSrcReg
__IOM uint32_t | ReqDstReg
uint32_t | Undefined_ReqDstReg
__IOM uint32_t | SglReqSrcReg
uint32_t | Undefined_SglReqSrcReg
__IOM uint32_t | SglReqDstReg
uint32_t | Undefined_SglReqDstReg
__IOM uint32_t | LstSrcReg
uint32_t | Undefined_LstSrcReg
__IOM uint32_t | LstDstReg
uint32_t | Undefined_LstDstReg
__IOM uint32_t | DmaCfgReg
uint32_t | Undefined_DmaCfgReg
__IOM uint32_t | ChEnReg
uint32_t | Undefined_ChEnReg

## 结构体成员变量说明

## ◆ CFGH

__IOM uint32_t CFGH

Channel x Configuration High Register, Address offset: 0x044, 0x09C, 0x0F4

## ◆ CFGL

__IOM uint32_t CFGL

Channel x Configuration Low Register, Address offset: 0x040, 0x098, 0x0F0

## ◆ ChEnReg

__IOM uint32_t ChEnReg

DMA Channel Enable Register, Address offset: 0x3A0

## ◆ ClearBlock

__OM uint32_t ClearBlock

Clear for IntBlock Interrupt, Address offset: 0x340

## ◆ ClearDstTran

__OM uint32_t ClearDstTran

Clear for IntDstTran Interrupt, Address offset: 0x350

## ◆ ClearErr

__OM uint32_t ClearErr

Clear for IntErr Interrupt, Address offset: 0x358

## ◆ ClearSrcTran

__OM uint32_t ClearSrcTran

Clear for IntSrcTran Interrupt, Address offset: 0x348

## ◆ ClearTfr

__OM uint32_t ClearTfr

Clear for IntTfr Interrupt, Address offset: 0x338

## ◆ CTLH

__IOM uint32_t CTLH

Channel x Control High Register, Address offset: 0x01C, 0x074, 0x0CC

## ◆ CTLL

__IOM uint32_t CTLL

Channel x Control Low Register, Address offset: 0x018, 0x070, 0x0C8

## ◆ DAR

__IOM uint32_t DAR

Channel x Destination Address Register, Address offset: 0x008, 0x060, 0x0B8

## ◆ DmaCfgReg

__IOM uint32_t DmaCfgReg

DMA Configuration Register, Address offset: 0x398

## ◆ DSR

__IOM uint32_t DSR

Channel x Destination Scatter Register, Address offset: 0x050, 0x0A8, 0x100

## ◆ LstDstReg

__IOM uint32_t LstDstReg

Last Destination Transaction Request Register, Address offset: 0x390

## ◆ LstSrcReg

__IOM uint32_t LstSrcReg

Last Source Transaction Request Register, Address offset: 0x388

## ◆ MaskBlock

__IOM uint32_t MaskBlock

Mask for IntBlock Interrupt, Address offset: 0x318

## ◆ MaskDstTran

__IOM uint32_t MaskDstTran

Mask for IntDstTran Interrupt, Address offset: 0x328

## ◆ MaskErr

__IOM uint32_t MaskErr

Mask for IntErr Interrupt, Address offset: 0x330

## ◆ MaskSrcTran

__IOM uint32_t MaskSrcTran

Mask for IntSrcTran Interrupt, Address offset: 0x320

## ◆ MaskTfr

__IOM uint32_t MaskTfr

Mask for IntTfr Interrupt, Address offset: 0x310

## ◆ RawBlock

__IM uint32_t RawBlock

Raw Status for IntBlock Interrupt, Address offset: 0x2C8

## ◆ RawDstTran

__IM uint32_t RawDstTran

Raw Status for IntDstTran Interrupt, Address offset: 0x2D8

## ◆ RawErr

__IM uint32_t RawErr

Raw Status for IntErr Interrupt, Address offset: 0x2E0

## ◆ RawSrcTran

__IM uint32_t RawSrcTran

Raw Status for IntSrcTran Interrupt, Address offset: 0x2D0

## ◆ RawTfr

__IM uint32_t RawTfr

Raw Status for IntTfr Interrupt, Address offset: 0x2C0

## ◆ ReqDstReg

__IOM uint32_t ReqDstReg

Destination Software Transaction Request Register, Address offset: 0x370

## ◆ ReqSrcReg

__IOM uint32_t ReqSrcReg

Source Software Transaction Request Register, Address offset: 0x368

## ◆ RESERVED0

uint32_t RESERVED0[2]

Reserved

## ◆ RESERVED1

uint32_t RESERVED1[8]

Reserved

## ◆ RESERVED2

uint32_t RESERVED2[110]

Reserved, 0x108 - 0x2BC

## ◆ SAR

__IOM uint32_t SAR

Channel x Source Address Register, Address offset: 0x000, 0x058, 0x0B0

## ◆ SglReqDstReg

__IOM uint32_t SglReqDstReg

Single Destination Transaction Request Register, Address offset: 0x380

## ◆ SglReqSrcReg

__IOM uint32_t SglReqSrcReg

Single Source Transaction Request Register, Address offset: 0x378

## ◆ SGR

__IOM uint32_t SGR

Channel x Source Gather Register, Address offset: 0x048, 0x0A0, 0x0F8

## ◆ StatusBlock

__IM uint32_t StatusBlock

Status for IntBlock Interrupt, Address offset: 0x2F0

## ◆ StatusDstTran

__IM uint32_t StatusDstTran

Status for IntDstTran Interrupt, Address offset: 0x300

## ◆ StatusErr

__IM uint32_t StatusErr

Status for IntErr Interrupt, Address offset: 0x308

## ◆ StatusInt

__IM uint32_t StatusInt

Status for each interrupt type, Address offset: 0x360

## ◆ StatusSrcTran

__IM uint32_t StatusSrcTran

Status for IntSrcTran Interrupt, Address offset: 0x2F8

## ◆ StatusTfr

__IM uint32_t StatusTfr

Status for IntTfr Interrupt, Address offset: 0x2E8

该结构体的文档由以下文件生成:

- mg32f10x.h