MG32F10x Standard Peripherals Firmware Library

成员变量
DWT_Type结构体 参考
Defines and Type Definitions » Data Watchpoint and Trace (DWT)

Structure type to access the Data Watchpoint and Trace Register (DWT). 更多...

`#include <core_cm3.h>`

## 成员变量
__IOM uint32_t | CTRL
__IOM uint32_t | CYCCNT
__IOM uint32_t | CPICNT
__IOM uint32_t | EXCCNT
__IOM uint32_t | SLEEPCNT
__IOM uint32_t | LSUCNT
__IOM uint32_t | FOLDCNT
__IM uint32_t | PCSR
__IOM uint32_t | COMP0
__IOM uint32_t | MASK0
__IOM uint32_t | FUNCTION0
uint32_t | RESERVED0 [1U]
__IOM uint32_t | COMP1
__IOM uint32_t | MASK1
__IOM uint32_t | FUNCTION1
uint32_t | RESERVED1 [1U]
__IOM uint32_t | COMP2
__IOM uint32_t | MASK2
__IOM uint32_t | FUNCTION2
uint32_t | RESERVED2 [1U]
__IOM uint32_t | COMP3
__IOM uint32_t | MASK3
__IOM uint32_t | FUNCTION3

## 详细描述

Structure type to access the Data Watchpoint and Trace Register (DWT).

## 结构体成员变量说明

## ◆ COMP0

__IOM uint32_t COMP0

Offset: 0x020 (R/W) Comparator Register 0

## ◆ COMP1

__IOM uint32_t COMP1

Offset: 0x030 (R/W) Comparator Register 1

## ◆ COMP2

__IOM uint32_t COMP2

Offset: 0x040 (R/W) Comparator Register 2

## ◆ COMP3

__IOM uint32_t COMP3

Offset: 0x050 (R/W) Comparator Register 3

## ◆ CPICNT

__IOM uint32_t CPICNT

Offset: 0x008 (R/W) CPI Count Register

## ◆ CTRL

__IOM uint32_t CTRL

Offset: 0x000 (R/W) Control Register

## ◆ CYCCNT

__IOM uint32_t CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

## ◆ EXCCNT

__IOM uint32_t EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

## ◆ FOLDCNT

__IOM uint32_t FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

## ◆ FUNCTION0

__IOM uint32_t FUNCTION0

Offset: 0x028 (R/W) Function Register 0

## ◆ FUNCTION1

__IOM uint32_t FUNCTION1

Offset: 0x038 (R/W) Function Register 1

## ◆ FUNCTION2

__IOM uint32_t FUNCTION2

Offset: 0x048 (R/W) Function Register 2

## ◆ FUNCTION3

__IOM uint32_t FUNCTION3

Offset: 0x058 (R/W) Function Register 3

## ◆ LSUCNT

__IOM uint32_t LSUCNT

Offset: 0x014 (R/W) LSU Count Register

## ◆ MASK0

__IOM uint32_t MASK0

Offset: 0x024 (R/W) Mask Register 0

## ◆ MASK1

__IOM uint32_t MASK1

Offset: 0x034 (R/W) Mask Register 1

## ◆ MASK2

__IOM uint32_t MASK2

Offset: 0x044 (R/W) Mask Register 2

## ◆ MASK3

__IOM uint32_t MASK3

Offset: 0x054 (R/W) Mask Register 3

## ◆ PCSR

__IM uint32_t PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

## ◆ SLEEPCNT

__IOM uint32_t SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register

该结构体的文档由以下文件生成:

- core_cm3.h