MG32F10x Standard Peripherals Firmware Library

成员变量
NVIC_Type结构体 参考
Defines and Type Definitions » Nested Vectored Interrupt Controller (NVIC)

Structure type to access the Nested Vectored Interrupt Controller (NVIC). 更多...

`#include <core_cm3.h>`

## 成员变量
__IOM uint32_t | ISER [8U]
uint32_t | RESERVED0 [24U]
__IOM uint32_t | ICER [8U]
uint32_t | RSERVED1 [24U]
__IOM uint32_t | ISPR [8U]
uint32_t | RESERVED2 [24U]
__IOM uint32_t | ICPR [8U]
uint32_t | RESERVED3 [24U]
__IOM uint32_t | IABR [8U]
uint32_t | RESERVED4 [56U]
__IOM uint8_t | IP [240U]
uint32_t | RESERVED5 [644U]
__OM uint32_t | STIR

## 详细描述

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

## 结构体成员变量说明

## ◆ IABR

__IOM uint32_t IABR[8U]

Offset: 0x200 (R/W) Interrupt Active bit Register

## ◆ ICER

__IOM uint32_t ICER[8U]

Offset: 0x080 (R/W) Interrupt Clear Enable Register

## ◆ ICPR

__IOM uint32_t ICPR[8U]

Offset: 0x180 (R/W) Interrupt Clear Pending Register

## ◆ IP

__IOM uint8_t IP[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

## ◆ ISER

__IOM uint32_t ISER[8U]

Offset: 0x000 (R/W) Interrupt Set Enable Register

## ◆ ISPR

__IOM uint32_t ISPR[8U]

Offset: 0x100 (R/W) Interrupt Set Pending Register

## ◆ STIR

__OM uint32_t STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

该结构体的文档由以下文件生成:

- core_cm3.h