MG32F10x Standard Peripherals Firmware Library

模块 | 结构体 | 宏定义 | 类型定义 | 枚举
Mg32f10x
CMSIS

## 模块
| Library_configuration_section
| Exported_macro

## 结构体
struct | GPIO_TypeDef
struct | TIM_TypeDef
struct | EXTI_TypeDef
struct | AFIO_TypeDef
struct | WWDG_TypeDef
struct | IWDG_TypeDef
struct | BKP_TypeDef
struct | RTC_TypeDef
struct | LED_TypeDef
struct | SFM_TypeDef
struct | ISO_TypeDef
struct | CACHE_TypeDef
struct | FMC_TypeDef
struct | SYS_TypeDef
struct | CRC_TypeDef
struct | UART_TypeDef
struct | DMAC_TypeDef
struct | SPI_TypeDef
struct | I2C_TypeDef
struct | I2S_TypeDef
struct | RNG_TypeDef
struct | USB_TypeDef
struct | ADC_TypeDef
struct | ANCTL_TypeDef
struct | RCC_TypeDef
struct | PWR_TypeDef
struct | DBGMCU_TypeDef

## 宏定义
#define | MHSI_VALUE (8000000)
#define | FHSI_VALUE (48000000)
#define | __CM3_REV 0x0200U /* Core revision r2p0 */
#define | __MPU_PRESENT 1 /* MG32F10x devices provide an MPU */
#define | __VTOR_PRESENT 1 /* VTOR present or not */
#define | __NVIC_PRIO_BITS 4 /* Number of Bits used for Priority Levels */
#define | __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#define | IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define | FLASH_BASE ((uint32_t)0x08000000UL)
#define | SRAM_BASE ((uint32_t)0x20000000UL)
#define | PERIPH_BASE ((uint32_t)0x40000000UL)
#define | SRAM_BB_BASE ((uint32_t)0x22000000UL)
#define | PERIPH_BB_BASE ((uint32_t)0x42000000UL)
#define | APB1PERIPH_BASE PERIPH_BASE
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x08000)
#define | AHBPERIPH_BASE (PERIPH_BASE + 0x10000)
#define | GPIOA_BASE (APB1PERIPH_BASE + 0x0000)
#define | GPIOB_BASE (APB1PERIPH_BASE + 0x0400)
#define | GPIOC_BASE (APB1PERIPH_BASE + 0x0800)
#define | GPIOD_BASE (APB1PERIPH_BASE + 0x0C00)
#define | AFIO_BASE (APB1PERIPH_BASE + 0x1400)
#define | EXTI_BASE (APB1PERIPH_BASE + 0x1800)
#define | TIM1_BASE (APB1PERIPH_BASE + 0x1C00)
#define | TIM2_BASE (APB1PERIPH_BASE + 0x2000)
#define | TIM3_BASE (APB1PERIPH_BASE + 0x2400)
#define | TIM4_BASE (APB1PERIPH_BASE + 0x2800)
#define | QSPI_BASE (APB1PERIPH_BASE + 0x3000)
#define | SPIS1_BASE (APB1PERIPH_BASE + 0x3400)
#define | UART1_BASE (APB1PERIPH_BASE + 0x3800)
#define | ADC_BASE (APB1PERIPH_BASE + 0x3C00)
#define | DMAC1_BASE (APB1PERIPH_BASE + 0x7C00)
#define | UART2_BASE (APB2PERIPH_BASE + 0x0000)
#define | UART3_BASE (APB2PERIPH_BASE + 0x0400)
#define | I2C1_BASE (APB2PERIPH_BASE + 0x0800)
#define | I2C2_BASE (APB2PERIPH_BASE + 0x0C00)
#define | SPIM2_BASE (APB2PERIPH_BASE + 0x1000)
#define | SPIS2_BASE (APB2PERIPH_BASE + 0x1400)
#define | WWDG_BASE (APB2PERIPH_BASE + 0x1800)
#define | I2S_BASE (APB2PERIPH_BASE + 0x3400)
#define | RNG_BASE (APB2PERIPH_BASE + 0x3800)
#define | LED_BASE (APB2PERIPH_BASE + 0x3C00)
#define | DMAC2_BASE (APB2PERIPH_BASE + 0x7C00)
#define | PWR_BASE (AHBPERIPH_BASE + 0x0000)
#define | ANCTL_BASE (AHBPERIPH_BASE + 0x0400)
#define | IWDG_BASE (AHBPERIPH_BASE + 0x0800)
#define | RCC_BASE (AHBPERIPH_BASE + 0x0C00)
#define | USB_BASE (AHBPERIPH_BASE + 0x4000)
#define | CRC_BASE (AHBPERIPH_BASE + 0x4800)
#define | SFM_BASE (AHBPERIPH_BASE + 0x4C00)
#define | CACHE_BASE (AHBPERIPH_BASE + 0x5400)
#define | RTC_BASE (AHBPERIPH_BASE + 0x5800)
#define | BKP_BASE (AHBPERIPH_BASE + 0x5C00)
#define | ISO_BASE (AHBPERIPH_BASE + 0x6000)
#define | SYS_BASE (AHBPERIPH_BASE + 0x6400)
#define | FMC_BASE (AHBPERIPH_BASE + 0x7800)
#define | DBGMCU_BASE (0xE0042000UL)
#define | GPIOA (( GPIO_TypeDef *) GPIOA_BASE)
#define | GPIOB (( GPIO_TypeDef *) GPIOB_BASE)
#define | GPIOC (( GPIO_TypeDef *) GPIOC_BASE)
#define | GPIOD (( GPIO_TypeDef *) GPIOD_BASE)
#define | AFIO (( AFIO_TypeDef *) AFIO_BASE)
#define | EXTI (( EXTI_TypeDef *) EXTI_BASE)
#define | TIM1 (( TIM_TypeDef *) TIM1_BASE)
#define | TIM2 (( TIM_TypeDef *) TIM2_BASE)
#define | TIM3 (( TIM_TypeDef *) TIM3_BASE)
#define | TIM4 (( TIM_TypeDef *) TIM4_BASE)
#define | QSPI (( SPI_TypeDef *) QSPI_BASE)
#define | SPIS1 (( SPI_TypeDef *) SPIS1_BASE)
#define | UART1 (( UART_TypeDef *) UART1_BASE)
#define | ADC (( ADC_TypeDef *) ADC_BASE)
#define | DMAC1 (( DMAC_TypeDef *) DMAC1_BASE)
#define | UART2 (( UART_TypeDef *) UART2_BASE)
#define | UART3 (( UART_TypeDef *) UART3_BASE)
#define | I2C1 (( I2C_TypeDef *) I2C1_BASE)
#define | I2C2 (( I2C_TypeDef *) I2C2_BASE)
#define | SPIM2 (( SPI_TypeDef *) SPIM2_BASE)
#define | SPIS2 (( SPI_TypeDef *) SPIS2_BASE)
#define | WWDG (( WWDG_TypeDef *) WWDG_BASE)
#define | I2S (( I2S_TypeDef *) I2S_BASE)
#define | RNG (( RNG_TypeDef *) RNG_BASE)
#define | LED (( LED_TypeDef *) LED_BASE)
#define | DMAC2 (( DMAC_TypeDef *) DMAC2_BASE)
#define | PWR (( PWR_TypeDef *) PWR_BASE)
#define | ANCTL (( ANCTL_TypeDef *) ANCTL_BASE)
#define | IWDG (( IWDG_TypeDef *) IWDG_BASE)
#define | RCC (( RCC_TypeDef *) RCC_BASE)
#define | USB (( USB_TypeDef *) USB_BASE)
#define | CRC (( CRC_TypeDef *) CRC_BASE)
#define | SFM (( SFM_TypeDef *) SFM_BASE)
#define | CACHE (( CACHE_TypeDef *) CACHE_BASE)
#define | RTC (( RTC_TypeDef *) RTC_BASE)
#define | BKP (( BKP_TypeDef *) BKP_BASE)
#define | ISO (( ISO_TypeDef *) ISO_BASE)
#define | SYS (( SYS_TypeDef *) SYS_BASE)
#define | FMC (( FMC_TypeDef *) FMC_BASE)
#define | DBGMCU (( DBGMCU_TypeDef *) DBGMCU_BASE)
#define | GPIO_MODER_MODER0_Pos (0U)
#define | GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos)
#define | GPIO_MODER_MODER1_Pos (2U)
#define | GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos)
#define | GPIO_MODER_MODER2_Pos (4U)
#define | GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos)
#define | GPIO_MODER_MODER3_Pos (6U)
#define | GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos)
#define | GPIO_MODER_MODER4_Pos (8U)
#define | GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos)
#define | GPIO_MODER_MODER5_Pos (10U)
#define | GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos)
#define | GPIO_MODER_MODER6_Pos (12U)
#define | GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos)
#define | GPIO_MODER_MODER7_Pos (14U)
#define | GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos)
#define | GPIO_MODER_MODER8_Pos (16U)
#define | GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos)
#define | GPIO_MODER_MODER9_Pos (18U)
#define | GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos)
#define | GPIO_MODER_MODER10_Pos (20U)
#define | GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos)
#define | GPIO_MODER_MODER11_Pos (22U)
#define | GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos)
#define | GPIO_MODER_MODER12_Pos (24U)
#define | GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos)
#define | GPIO_MODER_MODER13_Pos (26U)
#define | GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos)
#define | GPIO_MODER_MODER14_Pos (28U)
#define | GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos)
#define | GPIO_MODER_MODER15_Pos (30U)
#define | GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos)
#define | GPIO_OTYPER_OT0 (0x1U << 0)
#define | GPIO_OTYPER_OT1 (0x1U << 1)
#define | GPIO_OTYPER_OT2 (0x1U << 2)
#define | GPIO_OTYPER_OT3 (0x1U << 3)
#define | GPIO_OTYPER_OT4 (0x1U << 4)
#define | GPIO_OTYPER_OT5 (0x1U << 5)
#define | GPIO_OTYPER_OT6 (0x1U << 6)
#define | GPIO_OTYPER_OT7 (0x1U << 7)
#define | GPIO_OTYPER_OT8 (0x1U << 8)
#define | GPIO_OTYPER_OT9 (0x1U << 9)
#define | GPIO_OTYPER_OT10 (0x1U << 10)
#define | GPIO_OTYPER_OT11 (0x1U << 11)
#define | GPIO_OTYPER_OT12 (0x1U << 12)
#define | GPIO_OTYPER_OT13 (0x1U << 13)
#define | GPIO_OTYPER_OT14 (0x1U << 14)
#define | GPIO_OTYPER_OT15 (0x1U << 15)
#define | GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
#define | GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)
#define | GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
#define | GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)
#define | GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
#define | GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)
#define | GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
#define | GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)
#define | GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
#define | GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)
#define | GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
#define | GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)
#define | GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
#define | GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)
#define | GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
#define | GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)
#define | GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
#define | GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)
#define | GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
#define | GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)
#define | GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
#define | GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos)
#define | GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
#define | GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos)
#define | GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
#define | GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos)
#define | GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
#define | GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos)
#define | GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
#define | GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos)
#define | GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
#define | GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos)
#define | GPIO_PUPDR_PUPDR0_Pos (0U)
#define | GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos)
#define | GPIO_PUPDR_PUPDR1_Pos (2U)
#define | GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos)
#define | GPIO_PUPDR_PUPDR2_Pos (4U)
#define | GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos)
#define | GPIO_PUPDR_PUPDR3_Pos (6U)
#define | GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos)
#define | GPIO_PUPDR_PUPDR4_Pos (8U)
#define | GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos)
#define | GPIO_PUPDR_PUPDR5_Pos (10U)
#define | GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos)
#define | GPIO_PUPDR_PUPDR6_Pos (12U)
#define | GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos)
#define | GPIO_PUPDR_PUPDR7_Pos (14U)
#define | GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos)
#define | GPIO_PUPDR_PUPDR8_Pos (16U)
#define | GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos)
#define | GPIO_PUPDR_PUPDR9_Pos (18U)
#define | GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos)
#define | GPIO_PUPDR_PUPDR10_Pos (20U)
#define | GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos)
#define | GPIO_PUPDR_PUPDR11_Pos (22U)
#define | GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos)
#define | GPIO_PUPDR_PUPDR12_Pos (24U)
#define | GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos)
#define | GPIO_PUPDR_PUPDR13_Pos (26U)
#define | GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos)
#define | GPIO_PUPDR_PUPDR14_Pos (28U)
#define | GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos)
#define | GPIO_PUPDR_PUPDR15_Pos (30U)
#define | GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos)
#define | GPIO_IDR_IDR0 (0x1U << 0)
#define | GPIO_IDR_IDR1 (0x1U << 1)
#define | GPIO_IDR_IDR2 (0x1U << 2)
#define | GPIO_IDR_IDR3 (0x1U << 3)
#define | GPIO_IDR_IDR4 (0x1U << 4)
#define | GPIO_IDR_IDR5 (0x1U << 5)
#define | GPIO_IDR_IDR6 (0x1U << 6)
#define | GPIO_IDR_IDR7 (0x1U << 7)
#define | GPIO_IDR_IDR8 (0x1U << 8)
#define | GPIO_IDR_IDR9 (0x1U << 9)
#define | GPIO_IDR_IDR10 (0x1U << 10)
#define | GPIO_IDR_IDR11 (0x1U << 11)
#define | GPIO_IDR_IDR12 (0x1U << 12)
#define | GPIO_IDR_IDR13 (0x1U << 13)
#define | GPIO_IDR_IDR14 (0x1U << 14)
#define | GPIO_IDR_IDR15 (0x1U << 15)
#define | GPIO_ODR_ODR0 (0x1U << 0)
#define | GPIO_ODR_ODR1 (0x1U << 1)
#define | GPIO_ODR_ODR2 (0x1U << 2)
#define | GPIO_ODR_ODR3 (0x1U << 3)
#define | GPIO_ODR_ODR4 (0x1U << 4)
#define | GPIO_ODR_ODR5 (0x1U << 5)
#define | GPIO_ODR_ODR6 (0x1U << 6)
#define | GPIO_ODR_ODR7 (0x1U << 7)
#define | GPIO_ODR_ODR8 (0x1U << 8)
#define | GPIO_ODR_ODR9 (0x1U << 9)
#define | GPIO_ODR_ODR10 (0x1U << 10)
#define | GPIO_ODR_ODR11 (0x1U << 11)
#define | GPIO_ODR_ODR12 (0x1U << 12)
#define | GPIO_ODR_ODR13 (0x1U << 13)
#define | GPIO_ODR_ODR14 (0x1U << 14)
#define | GPIO_ODR_ODR15 (0x1U << 15)
#define | GPIO_BSRR_BS0 (0x1U << 0)
#define | GPIO_BSRR_BS1 (0x1U << 1)
#define | GPIO_BSRR_BS2 (0x1U << 2)
#define | GPIO_BSRR_BS3 (0x1U << 3)
#define | GPIO_BSRR_BS4 (0x1U << 4)
#define | GPIO_BSRR_BS5 (0x1U << 5)
#define | GPIO_BSRR_BS6 (0x1U << 6)
#define | GPIO_BSRR_BS7 (0x1U << 7)
#define | GPIO_BSRR_BS8 (0x1U << 8)
#define | GPIO_BSRR_BS9 (0x1U << 9)
#define | GPIO_BSRR_BS10 (0x1U << 10)
#define | GPIO_BSRR_BS11 (0x1U << 11)
#define | GPIO_BSRR_BS12 (0x1U << 12)
#define | GPIO_BSRR_BS13 (0x1U << 13)
#define | GPIO_BSRR_BS14 (0x1U << 14)
#define | GPIO_BSRR_BS15 (0x1U << 15)
#define | GPIO_BSRR_BR0 (0x1U << 16)
#define | GPIO_BSRR_BR1 (0x1U << 17)
#define | GPIO_BSRR_BR2 (0x1U << 18)
#define | GPIO_BSRR_BR3 (0x1U << 19)
#define | GPIO_BSRR_BR4 (0x1U << 20)
#define | GPIO_BSRR_BR5 (0x1U << 21)
#define | GPIO_BSRR_BR6 (0x1U << 22)
#define | GPIO_BSRR_BR7 (0x1U << 23)
#define | GPIO_BSRR_BR8 (0x1U << 24)
#define | GPIO_BSRR_BR9 (0x1U << 25)
#define | GPIO_BSRR_BR10 (0x1U << 26)
#define | GPIO_BSRR_BR11 (0x1U << 27)
#define | GPIO_BSRR_BR12 (0x1U << 28)
#define | GPIO_BSRR_BR13 (0x1U << 29)
#define | GPIO_BSRR_BR14 (0x1U << 30)
#define | GPIO_BSRR_BR15 (0x1U << 31)
#define | GPIO_LCKR_LCK0 (0x1U << 0)
#define | GPIO_LCKR_LCK1 (0x1U << 1)
#define | GPIO_LCKR_LCK2 (0x1U << 2)
#define | GPIO_LCKR_LCK3 (0x1U << 3)
#define | GPIO_LCKR_LCK4 (0x1U << 4)
#define | GPIO_LCKR_LCK5 (0x1U << 5)
#define | GPIO_LCKR_LCK6 (0x1U << 6)
#define | GPIO_LCKR_LCK7 (0x1U << 7)
#define | GPIO_LCKR_LCK8 (0x1U << 8)
#define | GPIO_LCKR_LCK9 (0x1U << 9)
#define | GPIO_LCKR_LCK10 (0x1U << 10)
#define | GPIO_LCKR_LCK11 (0x1U << 11)
#define | GPIO_LCKR_LCK12 (0x1U << 12)
#define | GPIO_LCKR_LCK13 (0x1U << 13)
#define | GPIO_LCKR_LCK14 (0x1U << 14)
#define | GPIO_LCKR_LCK15 (0x1U << 15)
#define | GPIO_LCKR_LCKK (0x1U << 16)
#define | GPIO_AFRL_AFR0_Pos (0U)
#define | GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos)
#define | GPIO_AFRL_AFR1_Pos (4U)
#define | GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos)
#define | GPIO_AFRL_AFR2_Pos (8U)
#define | GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos)
#define | GPIO_AFRL_AFR3_Pos (12U)
#define | GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos)
#define | GPIO_AFRL_AFR4_Pos (16U)
#define | GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos)
#define | GPIO_AFRL_AFR5_Pos (20U)
#define | GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos)
#define | GPIO_AFRL_AFR6_Pos (24U)
#define | GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos)
#define | GPIO_AFRL_AFR7_Pos (28U)
#define | GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos)
#define | GPIO_AFRH_AFR8_Pos (0U)
#define | GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos)
#define | GPIO_AFRH_AFR9_Pos (4U)
#define | GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos)
#define | GPIO_AFRH_AFR10_Pos (8U)
#define | GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos)
#define | GPIO_AFRH_AFR11_Pos (12U)
#define | GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos)
#define | GPIO_AFRH_AFR12_Pos (16U)
#define | GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos)
#define | GPIO_AFRH_AFR13_Pos (20U)
#define | GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos)
#define | GPIO_AFRH_AFR14_Pos (24U)
#define | GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos)
#define | GPIO_AFRH_AFR15_Pos (28U)
#define | GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos)
#define | GPIO_SMIT_SMIT0 (0x1U << 0)
#define | GPIO_SMIT_SMIT1 (0x1U << 1)
#define | GPIO_SMIT_SMIT2 (0x1U << 2)
#define | GPIO_SMIT_SMIT3 (0x1U << 3)
#define | GPIO_SMIT_SMIT4 (0x1U << 4)
#define | GPIO_SMIT_SMIT5 (0x1U << 5)
#define | GPIO_SMIT_SMIT6 (0x1U << 6)
#define | GPIO_SMIT_SMIT7 (0x1U << 7)
#define | GPIO_SMIT_SMIT8 (0x1U << 8)
#define | GPIO_SMIT_SMIT9 (0x1U << 9)
#define | GPIO_SMIT_SMIT10 (0x1U << 10)
#define | GPIO_SMIT_SMIT11 (0x1U << 11)
#define | GPIO_SMIT_SMIT12 (0x1U << 12)
#define | GPIO_SMIT_SMIT13 (0x1U << 13)
#define | GPIO_SMIT_SMIT14 (0x1U << 14)
#define | GPIO_SMIT_SMIT15 (0x1U << 15)
#define | GPIO_CURRENT_CURRENT0_Pos (0U)
#define | GPIO_CURRENT_CURRENT0_Msk (0x3U << GPIO_CURRENT_CURRENT0_Pos)
#define | GPIO_CURRENT_CURRENT1_Pos (2U)
#define | GPIO_CURRENT_CURRENT1_Msk (0x3U << GPIO_CURRENT_CURRENT1_Pos)
#define | GPIO_CURRENT_CURRENT2_Pos (4U)
#define | GPIO_CURRENT_CURRENT2_Msk (0x3U << GPIO_CURRENT_CURRENT2_Pos)
#define | GPIO_CURRENT_CURRENT3_Pos (6U)
#define | GPIO_CURRENT_CURRENT3_Msk (0x3U << GPIO_CURRENT_CURRENT3_Pos)
#define | GPIO_CURRENT_CURRENT4_Pos (8U)
#define | GPIO_CURRENT_CURRENT4_Msk (0x3U << GPIO_CURRENT_CURRENT4_Pos)
#define | GPIO_CURRENT_CURRENT5_Pos (10U)
#define | GPIO_CURRENT_CURRENT5_Msk (0x3U << GPIO_CURRENT_CURRENT5_Pos)
#define | GPIO_CURRENT_CURRENT6_Pos (12U)
#define | GPIO_CURRENT_CURRENT6_Msk (0x3U << GPIO_CURRENT_CURRENT6_Pos)
#define | GPIO_CURRENT_CURRENT7_Pos (14U)
#define | GPIO_CURRENT_CURRENT7_Msk (0x3U << GPIO_CURRENT_CURRENT7_Pos)
#define | GPIO_CURRENT_CURRENT8_Pos (16U)
#define | GPIO_CURRENT_CURRENT8_Msk (0x3U << GPIO_CURRENT_CURRENT8_Pos)
#define | GPIO_CURRENT_CURRENT9_Pos (18U)
#define | GPIO_CURRENT_CURRENT9_Msk (0x3U << GPIO_CURRENT_CURRENT9_Pos)
#define | GPIO_CURRENT_CURRENT10_Pos (20U)
#define | GPIO_CURRENT_CURRENT10_Msk (0x3U << GPIO_CURRENT_CURRENT10_Pos)
#define | GPIO_CURRENT_CURRENT11_Pos (22U)
#define | GPIO_CURRENT_CURRENT11_Msk (0x3U << GPIO_CURRENT_CURRENT11_Pos)
#define | GPIO_CURRENT_CURRENT12_Pos (24U)
#define | GPIO_CURRENT_CURRENT12_Msk (0x3U << GPIO_CURRENT_CURRENT12_Pos)
#define | GPIO_CURRENT_CURRENT13_Pos (26U)
#define | GPIO_CURRENT_CURRENT13_Msk (0x3U << GPIO_CURRENT_CURRENT13_Pos)
#define | GPIO_CURRENT_CURRENT14_Pos (28U)
#define | GPIO_CURRENT_CURRENT14_Msk (0x3U << GPIO_CURRENT_CURRENT14_Pos)
#define | GPIO_CURRENT_CURRENT15_Pos (30U)
#define | GPIO_CURRENT_CURRENT15_Msk (0x3U << GPIO_CURRENT_CURRENT15_Pos)
#define | GPIO_CFGMSK_CFGMSK0 (0x1U << 0)
#define | GPIO_CFGMSK_CFGMSK1 (0x1U << 1)
#define | GPIO_CFGMSK_CFGMSK2 (0x1U << 2)
#define | GPIO_CFGMSK_CFGMSK3 (0x1U << 3)
#define | GPIO_CFGMSK_CFGMSK4 (0x1U << 4)
#define | GPIO_CFGMSK_CFGMSK5 (0x1U << 5)
#define | GPIO_CFGMSK_CFGMSK6 (0x1U << 6)
#define | GPIO_CFGMSK_CFGMSK7 (0x1U << 7)
#define | GPIO_CFGMSK_CFGMSK8 (0x1U << 8)
#define | GPIO_CFGMSK_CFGMSK9 (0x1U << 9)
#define | GPIO_CFGMSK_CFGMSK10 (0x1U << 10)
#define | GPIO_CFGMSK_CFGMSK11 (0x1U << 11)
#define | GPIO_CFGMSK_CFGMSK12 (0x1U << 12)
#define | GPIO_CFGMSK_CFGMSK13 (0x1U << 13)
#define | GPIO_CFGMSK_CFGMSK14 (0x1U << 14)
#define | GPIO_CFGMSK_CFGMSK15 (0x1U << 15)
#define | UART_IER_RDAIE (0x1U << 0)
#define | UART_IER_THREIE (0x1U << 1)
#define | UART_IER_RLSIE (0x1U << 2)
#define | UART_IER_MSIE (0x1U << 3)
#define | UART_IER_LSRCLRMD (0x1U << 4)
#define | UART_IER_PTIME (0x1U << 7)
#define | UART_IIR_INTID_Msk (0xFU)
#define | UART_IIR_INTID_MSI (0x0U)
#define | UART_IIR_INTID_NONE (0x1U)
#define | UART_IIR_INTID_THRE (0x2U)
#define | UART_IIR_INTID_RDA (0x4U)
#define | UART_IIR_INTID_RLS (0x6U)
#define | UART_IIR_INTID_BUSY (0x7U)
#define | UART_IIR_INTID_CTI (0xCU)
#define | UART_IIR_FIFOSE_Pos (6U)
#define | UART_IIR_FIFOSE_Msk (0x3U << UART_IIR_FIFOSE_Pos)
#define | UART_FCR_FIFOE (0x1U << 0)
#define | UART_FCR_RFIFOR (0x1U << 1)
#define | UART_FCR_XFIFOR (0x1U << 2)
#define | UART_FCR_TET_0 (0x0U << 4)
#define | UART_FCR_TET_2 (0x1U << 4)
#define | UART_FCR_TET_4 (0x2U << 4)
#define | UART_FCR_TET_8 (0x3U << 4)
#define | UART_FCR_RT_1 (0x0U << 6)
#define | UART_FCR_RT_4 (0x1U << 6)
#define | UART_FCR_RT_8 (0x2U << 6)
#define | UART_FCR_RT_14 (0x3U << 6)
#define | UART_LCR_WLS_Msk (0x3U << 0)
#define | UART_LCR_WLS_5BIT (0x0U << 0)
#define | UART_LCR_WLS_6BIT (0x1U << 0)
#define | UART_LCR_WLS_7BIT (0x2U << 0)
#define | UART_LCR_WLS_8BIT (0x3U << 0)
#define | UART_LCR_SBS_Msk (0x1U << 2)
#define | UART_LCR_SBS_1BIT (0x0U << 2)
#define | UART_LCR_SBS_2BIT (0x1U << 2)
#define | UART_LCR_PARITY_Msk (0x7U << 3)
#define | UART_LCR_PARITY_NONE (0x0U << 3)
#define | UART_LCR_PARITY_ODD (0x1U << 3)
#define | UART_LCR_PARITY_EVEN (0x3U << 3)
#define | UART_LCR_PARITY_MARK (0x5U << 3)
#define | UART_LCR_PARITY_SPACE (0x7U << 3)
#define | UART_LCR_BC (0x1U << 6)
#define | UART_LCR_DLAB (0x1U << 7)
#define | UART_MCR_RTS (0x1U << 1)
#define | UART_MCR_LB (0x1U << 4)
#define | UART_MCR_AFCE (0x1U << 5)
#define | UART_MCR_SIRE (0x1U << 6)
#define | UART_LSR_DR (0x1U << 0)
#define | UART_LSR_OE (0x1U << 1)
#define | UART_LSR_PE (0x1U << 2)
#define | UART_LSR_FE (0x1U << 3)
#define | UART_LSR_BI (0x1U << 4)
#define | UART_LSR_THRE (0x1U << 5)
#define | UART_LSR_TEMT (0x1U << 6)
#define | UART_LSR_RFE (0x1U << 7)
#define | UART_LSR_ADDR_RCVD (0x1U << 8)
#define | UART_MSR_DCTS (0x1U << 0)
#define | UART_MSR_CTS (0x1U << 4)
#define | UART_USR_BUSY (0x1U << 0)
#define | UART_USR_TFNF (0x1U << 1)
#define | UART_USR_TFE (0x1U << 2)
#define | UART_USR_RFNE (0x1U << 3)
#define | UART_USR_RFF (0x1U << 4)
#define | UART_SRR_UR (0x1U << 0)
#define | UART_SRR_RFR (0x1U << 1)
#define | UART_SRR_XFR (0x1U << 2)
#define | UART_SRTS_SRTS (0x1U << 0)
#define | UART_SBCR_SBCB (0x1U << 0)
#define | UART_SDMAM_SDMAM (0x1U << 0)
#define | UART_SFE_SFE (0x1U << 0)
#define | UART_SRT_LEV0 (0x0U)
#define | UART_SRT_LEV1 (0x1U)
#define | UART_SRT_LEV2 (0x2U)
#define | UART_SRT_LEV3 (0x3U)
#define | UART_STET_LEV0 (0x0U)
#define | UART_STET_LEV1 (0x1U)
#define | UART_STET_LEV2 (0x2U)
#define | UART_STET_LEV3 (0x3U)
#define | UART_HTX_HTX (0x1U << 0)
#define | UART_DMASA (0x1U << 0)
#define | UART_EXTLCR_WLS_E (0x1U << 0)
#define | UART_EXTLCR_ADDR_MATCH (0x1U << 1)
#define | UART_EXTLCR_SEND_ADDR (0x1U << 2)
#define | UART_EXTLCR_TRANSMIT_MODE (0x1U << 3)
#define | CRC_MODE_CRC_POLY_Msk (0x3U << 0)
#define | CRC_MODE_CRC_POLY_CRC8 (0x0U << 0)
#define | CRC_MODE_CRC_POLY_CCITT (0x1U << 0)
#define | CRC_MODE_CRC_POLY_CRC16 (0x2U << 0)
#define | CRC_MODE_CRC_POLY_CRC32 (0x3U << 0)
#define | CRC_MODE_BIT_RVS_WR (0x1U << 2)
#define | CRC_MODE_CMPL_WR (0x1U << 3)
#define | CRC_MODE_BIT_RVS_SUM (0x1U << 4)
#define | CRC_MODE_CMPL_SUM (0x1U << 5)
#define | CRC_MODE_SEED_OP (0x1U << 6)
#define | CRC_MODE_SEED_SET (0x1U << 7)
#define | SFM_CTRL_EXP_RATE_Msk (0x7U << 0)
#define | SFM_CTRL_EXP_RATE_1 (0x0U << 0)
#define | SFM_CTRL_EXP_RATE_2 (0x1U << 0)
#define | SFM_CTRL_EXP_RATE_3 (0x2U << 0)
#define | SFM_CTRL_EXP_RATE_4 (0x3U << 0)
#define | SFM_CTRL_EXP_RATE_5 (0x4U << 0)
#define | SFM_CTRL_EXP_RATE_6 (0x5U << 0)
#define | SFM_CTRL_EXP_RATE_7 (0x6U << 0)
#define | SFM_CTRL_EXP_RATE_8 (0x7U << 0)
#define | SFM_CTRL_EXP_EN (0x1U << 3)
#define | SFM_USBPSDCSR_SE0F (0x1U << 0)
#define | SFM_USBPSDCSR_JSTATF (0x1U << 1)
#define | SFM_USBPSDCSR_KSTATF (0x1U << 2)
#define | SFM_USBPSDCSR_SE1F (0x1U << 3)
#define | SFM_USBPSDCSR_SE0EN (0x1U << 8)
#define | SFM_USBPSDCSR_JSTATEN (0x1U << 9)
#define | SFM_USBPSDCSR_KSTATEN (0x1U << 10)
#define | SFM_USBPSDCSR_SE1EN (0x1U << 11)
#define | DMAC_CTLL_INT_EN (0x1U << 0)
#define | DMAC_CTLL_DST_TR_WIDTH_Msk (0x7U << 1)
#define | DMAC_CTLL_DST_TR_WIDTH_8 (0x0U << 1)
#define | DMAC_CTLL_DST_TR_WIDTH_16 (0x1U << 1)
#define | DMAC_CTLL_DST_TR_WIDTH_32 (0x2U << 1)
#define | DMAC_CTLL_SRC_TR_WIDTH_Msk (0x7U << 4)
#define | DMAC_CTLL_SRC_TR_WIDTH_8 (0x0U << 4)
#define | DMAC_CTLL_SRC_TR_WIDTH_16 (0x1U << 4)
#define | DMAC_CTLL_SRC_TR_WIDTH_32 (0x2U << 4)
#define | DMAC_CTLL_DINC_Msk (0x3U << 7)
#define | DMAC_CTLL_DINC_INC (0x0U << 7)
#define | DMAC_CTLL_DINC_DEC (0x1U << 7)
#define | DMAC_CTLL_DINC_NO (0x2U << 7)
#define | DMAC_CTLL_SINC_Msk (0x3U << 9)
#define | DMAC_CTLL_SINC_INC (0x0U << 9)
#define | DMAC_CTLL_SINC_DEC (0x1U << 9)
#define | DMAC_CTLL_SINC_NO (0x2U << 9)
#define | DMAC_CTLL_DEST_MSIZE_Msk (0x7U << 11)
#define | DMAC_CTLL_DEST_MSIZE_1 (0x0U << 11)
#define | DMAC_CTLL_DEST_MSIZE_4 (0x1U << 11)
#define | DMAC_CTLL_DEST_MSIZE_8 (0x2U << 11)
#define | DMAC_CTLL_DEST_MSIZE_16 (0x3U << 11)
#define | DMAC_CTLL_DEST_MSIZE_32 (0x4U << 11)
#define | DMAC_CTLL_DEST_MSIZE_64 (0x5U << 11)
#define | DMAC_CTLL_DEST_MSIZE_128 (0x6U << 11)
#define | DMAC_CTLL_DEST_MSIZE_256 (0x7U << 11)
#define | DMAC_CTLL_SRC_MSIZE_Msk (0x7U << 14)
#define | DMAC_CTLL_SRC_MSIZE_1 (0x0U << 14)
#define | DMAC_CTLL_SRC_MSIZE_4 (0x1U << 14)
#define | DMAC_CTLL_SRC_MSIZE_8 (0x2U << 14)
#define | DMAC_CTLL_SRC_MSIZE_16 (0x3U << 14)
#define | DMAC_CTLL_SRC_MSIZE_32 (0x4U << 14)
#define | DMAC_CTLL_SRC_MSIZE_64 (0x5U << 14)
#define | DMAC_CTLL_SRC_MSIZE_128 (0x6U << 14)
#define | DMAC_CTLL_SRC_MSIZE_256 (0x7U << 14)
#define | DMAC_CTLL_SRC_GATHER_EN (0x1U << 17)
#define | DMAC_CTLL_DST_SCATTER_EN (0x1U << 18)
#define | DMAC_CTLL_TT_FC_Msk (0x7U << 20)
#define | DMAC_CTLL_TT_FC_M2M_DMAC (0x0U << 20)
#define | DMAC_CTLL_TT_FC_M2P_DMAC (0x1U << 20)
#define | DMAC_CTLL_TT_FC_P2M_DMAC (0x2U << 20)
#define | DMAC_CTLL_TT_FC_P2P_DMAC (0x3U << 20)
#define | DMAC_CTLL_TT_FC_P2M_PERIPH (0x4U << 20)
#define | DMAC_CTLL_TT_FC_P2P_SRC_PERIPH (0x5U << 20)
#define | DMAC_CTLL_TT_FC_M2P_PERIPH (0x6U << 20)
#define | DMAC_CTLL_TT_FC_P2P_DST_PERIPH (0x7U << 20)
#define | DMAC_CTLL_LLP_DST_EN (0x1U << 27)
#define | DMAC_CTLL_LLP_SRC_EN (0x1U << 28)
#define | DMAC_CTLH_BLOCK_TS_Msk (0xFFFU)
#define | DMAC_CTLH_DONE (0x1U << 12)
#define | DMAC_CFGL_CH_PRIOR_Msk (0x7U << 5)
#define | DMAC_CFGL_CH_SUSP (0x1U << 8)
#define | DMAC_CFGL_FIFO_EMPTY (0x1U << 9)
#define | DMAC_CFGL_HS_SEL_DST (0x1U << 10)
#define | DMAC_CFGL_HS_SEL_SRC (0x1U << 11)
#define | DMAC_CFGL_DST_HS_POL (0x1U << 18)
#define | DMAC_CFGL_SRC_HS_POL (0x1U << 19)
#define | DMAC_CFGL_RELOAD_SRC (0x1U << 30)
#define | DMAC_CFGL_RELOAD_DST (0x1U << 31)
#define | DMAC_CFGH_FIFO_MODE (0x1U << 1)
#define | DMAC_CFGH_DS_UPD_EN (0x1U << 5)
#define | DMAC_CFGH_SS_UPD_EN (0x1U << 6)
#define | DMAC_CFGH_SRC_PER_Msk (0xFU << 7)
#define | DMAC_CFGH_DEST_PER_Msk (0xFU << 11)
#define | I2C_CON_MASTER_MODE (0x1U << 0)
#define | I2C_CON_SPEED_Msk (0x3U << 1)
#define | I2C_CON_SPEED_STANDARD (0x1U << 1)
#define | I2C_CON_SPEED_FAST (0x2U << 1)
#define | I2C_CON_SPEED_HIGH (0x3U << 1)
#define | I2C_CON_10BITADDR_SLAVE (0x1U << 3)
#define | I2C_CON_10BITADDR_MASTER (0x1U << 4)
#define | I2C_CON_RESTART_EN (0x1U << 5)
#define | I2C_CON_SLAVE_DISABLE (0x1U << 6)
#define | I2C_CON_STOP_DET_IFADDRESSED (0x1U << 7)
#define | I2C_CON_TX_EMPTY_CTRL (0x1U << 8)
#define | I2C_CON_RX_FIFO_FULL_HLD_CTRL (0x1U << 9)
#define | I2C_CON_STOP_DET_IF_MASTER_ACTIVE (0x1U << 10)
#define | I2C_CON_BUS_CLEAR_FEATURE_CTRL (0x1U << 11)
#define | I2C_CON_OPTIONAL_SAR_CTRL (0x1U << 16)
#define | I2C_CON_SMBUS_SLAVE_QUICK_EN (0x1U << 17)
#define | I2C_CON_SMBUS_ARP_EN (0x1U << 18)
#define | I2C_CON_SMBUS_PERSISTANT_SLV_ADDR_EN (0x1U << 19)
#define | I2C_TAR_TAR_Msk (0x3FFU)
#define | I2C_TAR_GC_OR_START (0x1U << 10)
#define | I2C_TAR_SPECIAL (0x1U << 11)
#define | I2C_TAR_10BITADDR_MASTER (0x1U << 12)
#define | I2C_TAR_DEVICE_ID (0x1U << 13)
#define | I2C_TAR_SMBUS_QUICK_CMD (0x1U << 16)
#define | I2C_DATA_CMD_DAT_Msk (0xFFU)
#define | I2C_DATA_CMD_READ (0x1U << 8)
#define | I2C_DATA_CMD_STOP (0x1U << 9)
#define | I2C_DATA_CMD_RESTART (0x1U << 10)
#define | I2C_DATA_CMD_FIRST_DATA_BYTE (0x1U << 11)
#define | I2C_INTR_RX_UNDER (0x1U << 0)
#define | I2C_INTR_RX_OVER (0x1U << 1)
#define | I2C_INTR_RX_FULL (0x1U << 2)
#define | I2C_INTR_TX_OVER (0x1U << 3)
#define | I2C_INTR_TX_EMPTY (0x1U << 4)
#define | I2C_INTR_RD_REQ (0x1U << 5)
#define | I2C_INTR_TX_ABRT (0x1U << 6)
#define | I2C_INTR_RX_DONE (0x1U << 7)
#define | I2C_INTR_ACTIVITY (0x1U << 8)
#define | I2C_INTR_STOP_DET (0x1U << 9)
#define | I2C_INTR_START_DET (0x1U << 10)
#define | I2C_INTR_GEN_CALL (0x1U << 11)
#define | I2C_INTR_RESTART_DET (0x1U << 12)
#define | I2C_INTR_SCL_STUCK_AT_LOW (0x1U << 14)
#define | I2C_ENABLE_ENABLE (0x1U << 0)
#define | I2C_ENABLE_ABORT (0x1U << 1)
#define | I2C_ENABLE_TX_CMD_BLOCK (0x1U << 2)
#define | I2C_ENABLE_SDA_STUCK_RECOVERY_ENA (0x1U << 3)
#define | I2C_ENABLE_SMBUS_CLK_RESET (0x1U << 16)
#define | I2C_ENABLE_SMBUS_SUSPEND_EN (0x1U << 17)
#define | I2C_ENABLE_SMBUS_ALERT_EN (0x1U << 18)
#define | I2C_STATUS_ACTIVITY (0x1U << 0)
#define | I2C_STATUS_TFNF (0x1U << 1)
#define | I2C_STATUS_TFE (0x1U << 2)
#define | I2C_STATUS_RFNE (0x1U << 3)
#define | I2C_STATUS_RFF (0x1U << 4)
#define | I2C_STATUS_MST_ACTIVITY (0x1U << 5)
#define | I2C_STATUS_SLV_ACTIVITY (0x1U << 6)
#define | I2C_STATUS_MST_HOLD_TX_FIFO_EMPTY (0x1U << 7)
#define | I2C_STATUS_MST_HOLD_RX_FIFO_FULL (0x1U << 8)
#define | I2C_STATUS_SLV_HOLD_TX_FIFO_EMPTY (0x1U << 9)
#define | I2C_STATUS_SLV_HOLD_RX_FIFO_FULL (0x1U << 10)
#define | I2C_STATUS_SDA_STUCK_NOT_RECOVERED (0x1U << 11)
#define | I2C_STATUS_SMBUS_QUICK_CMD_BIT (0x1U << 16)
#define | I2C_STATUS_SMBUS_SLAVE_ADDR_VALID (0x1U << 17)
#define | I2C_STATUS_SMBUS_SLAVE_ADDR_RESOLVED (0x1U << 18)
#define | I2C_STATUS_SMBUS_SUSPEND_STATUS (0x1U << 19)
#define | I2C_STATUS_SMBUS_ALERT_STATUS (0x1U << 20)
#define | I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK (0x1U << 0)
#define | I2C_TX_ABRT_SOURCE_10ADDR1_NOACK (0x1U << 1)
#define | I2C_TX_ABRT_SOURCE_10ADDR2_NOACK (0x1U << 2)
#define | I2C_TX_ABRT_SOURCE_TXDATA_NOACK (0x1U << 3)
#define | I2C_TX_ABRT_SOURCE_GCALL_NOACK (0x1U << 4)
#define | I2C_TX_ABRT_SOURCE_GCALL_READ (0x1U << 5)
#define | I2C_TX_ABRT_SOURCE_HS_ACKDET (0x1U << 6)
#define | I2C_TX_ABRT_SOURCE_SBYTE_ACKDET (0x1U << 7)
#define | I2C_TX_ABRT_SOURCE_HS_NORSTRT (0x1U << 8)
#define | I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT (0x1U << 9)
#define | I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT (0x1U << 10)
#define | I2C_TX_ABRT_SOURCE_MASTER_DIS (0x1U << 11)
#define | I2C_TX_ABRT_SOURCE_LOST (0x1U << 12)
#define | I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO (0x1U << 13)
#define | I2C_TX_ABRT_SOURCE_SLV_ARBLOST (0x1U << 14)
#define | I2C_TX_ABRT_SOURCE_SLVRD_INTX (0x1U << 15)
#define | I2C_TX_ABRT_SOURCE_USER_ABRT (0x1U << 16)
#define | I2C_TX_ABRT_SOURCE_SDA_STUCK_AT_LOW (0x1U << 17)
#define | I2C_TX_ABRT_SOURCE_DEVICE_NOACK (0x1U << 18)
#define | I2C_TX_ABRT_SOURCE_DEVICE_SLVADDR_NOACK (0x1U << 19)
#define | I2C_TX_ABRT_SOURCE_DEVICE_WRITE (0x1U << 20)
#define | I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk (0xFF800000U)
#define | I2C_SLV_DATA_NACK_ONLY_NACK (0x1U << 0)
#define | I2C_DMA_CR_RDMAE (0x1U << 0)
#define | I2C_DMA_CR_TDMAE (0x1U << 1)
#define | I2C_ENABLE_STATUS_IC_EN (0x1U << 0)
#define | I2C_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY (0x1U << 1)
#define | I2C_ENABLE_STATUS_SLV_RX_DATA_LOST (0x1U << 2)
#define | I2C_SMBUS_INTR_SLV_CLOCK_EXTND_TIMEOUT (0x1U << 0)
#define | I2C_SMBUS_INTR_MST_CLOCK_EXTND_TIMEOUT (0x1U << 1)
#define | I2C_SMBUS_INTR_QUICK_CMD_DET (0x1U << 2)
#define | I2C_SMBUS_INTR_HOST_NTFY_MST_DET (0x1U << 3)
#define | I2C_SMBUS_INTR_ARP_PREPARE_CMD_DET (0x1U << 4)
#define | I2C_SMBUS_INTR_ARP_RST_CMD_DET (0x1U << 5)
#define | I2C_SMBUS_INTR_ARP_GET_UDID_CMD_DET (0x1U << 6)
#define | I2C_SMBUS_INTR_ARP_ASSGN_ADDR_CMD_DET (0x1U << 7)
#define | I2C_SMBUS_INTR_SLV_RX_PEC_NACK (0x1U << 8)
#define | I2C_SMBUS_INTR_SMBUS_SUSPEND_DET (0x1U << 9)
#define | I2C_SMBUS_INTR_SMBUS_ALERT_DET (0x1U << 10)
#define | SPI_CR0_DFS_Msk (0xFU << 0)
#define | SPI_CR0_DFS_4BITS (0x3U << 0)
#define | SPI_CR0_DFS_5BITS (0x4U << 0)
#define | SPI_CR0_DFS_6BITS (0x5U << 0)
#define | SPI_CR0_DFS_7BITS (0x6U << 0)
#define | SPI_CR0_DFS_8BITS (0x7U << 0)
#define | SPI_CR0_DFS_9BITS (0x8U << 0)
#define | SPI_CR0_DFS_10BITS (0x9U << 0)
#define | SPI_CR0_DFS_11BITS (0xAU << 0)
#define | SPI_CR0_DFS_12BITS (0xBU << 0)
#define | SPI_CR0_DFS_13BITS (0xCU << 0)
#define | SPI_CR0_DFS_14BITS (0xDU << 0)
#define | SPI_CR0_DFS_15BITS (0xEU << 0)
#define | SPI_CR0_DFS_16BITS (0xFU << 0)
#define | SPI_CR0_FRF_Msk (0x3U << 4)
#define | SPI_CR0_FRF_SPI (0x0U << 4)
#define | SPI_CR0_FRF_SSP (0x1U << 4)
#define | SPI_CR0_FRF_NS (0x2U << 4)
#define | SPI_CR0_CPHA (0x1U << 6)
#define | SPI_CR0_CPOL (0x1U << 7)
#define | SPI_CR0_TMOD_Msk (0x3U << 8)
#define | SPI_CR0_TMOD_TX_AND_RX (0x0U << 8)
#define | SPI_CR0_TMOD_TX_ONLY (0x1U << 8)
#define | SPI_CR0_TMOD_RX_ONLY (0x2U << 8)
#define | SPI_CR0_TMOD_EEPROM_READ (0x3U << 8)
#define | SPI_CR0_SLV_OE (0x1U << 10)
#define | SPI_CR0_SRL (0x1U << 11)
#define | SPI_CR0_CFS_Msk (0xFU << 12)
#define | SPI_CR0_CFS_01_BIT (0x0U << 12)
#define | SPI_CR0_CFS_02_BIT (0x1U << 12)
#define | SPI_CR0_CFS_03_BIT (0x2U << 12)
#define | SPI_CR0_CFS_04_BIT (0x3U << 12)
#define | SPI_CR0_CFS_05_BIT (0x4U << 12)
#define | SPI_CR0_CFS_06_BIT (0x5U << 12)
#define | SPI_CR0_CFS_07_BIT (0x6U << 12)
#define | SPI_CR0_CFS_08_BIT (0x7U << 12)
#define | SPI_CR0_CFS_09_BIT (0x8U << 12)
#define | SPI_CR0_CFS_10_BIT (0x9U << 12)
#define | SPI_CR0_CFS_11_BIT (0xAU << 12)
#define | SPI_CR0_CFS_12_BIT (0xBU << 12)
#define | SPI_CR0_CFS_13_BIT (0xCU << 12)
#define | SPI_CR0_CFS_14_BIT (0xDU << 12)
#define | SPI_CR0_CFS_15_BIT (0xEU << 12)
#define | SPI_CR0_CFS_16_BIT (0xFU << 12)
#define | SPI_CR0_SPI_MODE_Msk (0x3U << 21)
#define | SPI_CR0_SPI_MODE_STD (0x0U << 21)
#define | SPI_CR0_SPI_MODE_DUAL (0x1U << 21)
#define | SPI_CR0_SPI_MODE_QUAD (0x2U << 21)
#define | SPI_CR0_SPI_MODE_OCTAL (0x3U << 21)
#define | SPI_CR0_SSTE (0x1U << 24)
#define | SPI_CR1_NDF_Msk (0xFFFFU)
#define | SPI_SPIENR_SPI_EN (0x1U << 0)
#define | SPI_MWCR_MWMOD (0x1U << 0)
#define | SPI_MWCR_MDD (0x1U << 1)
#define | SPI_MWCR_MHS (0x1U << 2)
#define | SPI_SER_Msk (0x7U << 0)
#define | SPI_SER_SE0 (0x1U << 0)
#define | SPI_SER_SE1 (0x1U << 1)
#define | SPI_SER_SE2 (0x1U << 2)
#define | SPI_BAUDR_SCKDV_Msk (0xFFFFU)
#define | SPI_SR_BUSY (0x1U << 0)
#define | SPI_SR_TFNF (0x1U << 1)
#define | SPI_SR_TFE (0x1U << 2)
#define | SPI_SR_RFNE (0x1U << 3)
#define | SPI_SR_RFF (0x1U << 4)
#define | SPI_SR_TXERR (0x1U << 5)
#define | SPI_SR_DCOL (0x1U << 6)
#define | SPI_IER_TXEIE (0x1U << 0)
#define | SPI_IER_TXOIE (0x1U << 1)
#define | SPI_IER_RXUIE (0x1U << 2)
#define | SPI_IER_RXOIE (0x1U << 3)
#define | SPI_IER_RXFIE (0x1U << 4)
#define | SPI_IER_MSTIE (0x1U << 5)
#define | SPI_ISR_TXEIS (0x1U << 0)
#define | SPI_ISR_TXOIS (0x1U << 1)
#define | SPI_ISR_RXUIS (0x1U << 2)
#define | SPI_ISR_RXOIS (0x1U << 3)
#define | SPI_ISR_RXFIS (0x1U << 4)
#define | SPI_ISR_MSTIS (0x1U << 5)
#define | SPI_RISR_TXEIR (0x1U << 0)
#define | SPI_RISR_TXOIR (0x1U << 1)
#define | SPI_RISR_RXUIR (0x1U << 2)
#define | SPI_RISR_RXOIR (0x1U << 3)
#define | SPI_RISR_RXFIR (0x1U << 4)
#define | SPI_RISR_MSTIR (0x1U << 5)
#define | SPI_DMACR_RDMAE (0x1U << 0)
#define | SPI_DMACR_TDMAE (0x1U << 1)
#define | SPI_ESPICR_TRANST_Msk (0x3U << 0)
#define | SPI_ESPICR_ADDRL_Msk (0xFU << 2)
#define | SPI_ESPICR_ADDRL_0BIT (0x0U << 2)
#define | SPI_ESPICR_ADDRL_4BIT (0x1U << 2)
#define | SPI_ESPICR_ADDRL_8BIT (0x2U << 2)
#define | SPI_ESPICR_ADDRL_12BIT (0x3U << 2)
#define | SPI_ESPICR_ADDRL_16BIT (0x4U << 2)
#define | SPI_ESPICR_ADDRL_20BIT (0x5U << 2)
#define | SPI_ESPICR_ADDRL_24BIT (0x6U << 2)
#define | SPI_ESPICR_ADDRL_28BIT (0x7U << 2)
#define | SPI_ESPICR_ADDRL_32BIT (0x8U << 2)
#define | SPI_ESPICR_ADDRL_36BIT (0x9U << 2)
#define | SPI_ESPICR_ADDRL_40BIT (0xAU << 2)
#define | SPI_ESPICR_ADDRL_44BIT (0xBU << 2)
#define | SPI_ESPICR_ADDRL_48BIT (0xCU << 2)
#define | SPI_ESPICR_ADDRL_52BIT (0xDU << 2)
#define | SPI_ESPICR_ADDRL_56BIT (0xEU << 2)
#define | SPI_ESPICR_ADDRL_60BIT (0xFU << 2)
#define | SPI_ESPICR_INSTL_Msk (0x3U << 8)
#define | SPI_ESPICR_INSTL_0BIT (0x0U << 8)
#define | SPI_ESPICR_INSTL_4BIT (0x1U << 8)
#define | SPI_ESPICR_INSTL_8BIT (0x2U << 8)
#define | SPI_ESPICR_INSTL_16BIT (0x3U << 8)
#define | SPI_ESPICR_WCYC_Msk (0x1FU << 11)
#define | I2S_IER_IEN (0x1U << 0)
#define | I2S_IRER_RXEN (0x1U << 0)
#define | I2S_ITER_TXEN (0x1U << 0)
#define | I2S_CER_CLKEN (0x1U << 0)
#define | I2S_CCR_SCLKG_Msk (0x7U << 0)
#define | I2S_CCR_SCLKG_NONE (0x0U << 0)
#define | I2S_CCR_SCLKG_12 (0x1U << 0)
#define | I2S_CCR_SCLKG_16 (0x2U << 0)
#define | I2S_CCR_SCLKG_20 (0x3U << 0)
#define | I2S_CCR_SCLKG_24 (0x4U << 0)
#define | I2S_CCR_WSS_Msk (0x3U << 3)
#define | I2S_CCR_WSS_16 (0x0U << 3)
#define | I2S_CCR_WSS_24 (0x1U << 3)
#define | I2S_CCR_WSS_32 (0x2U << 3)
#define | I2S_RXFFR_RXFFR (0x1U << 0)
#define | I2S_TXFFR_TXFFR (0x1U << 0)
#define | USB_FADDR_FADDR_Msk (0x7FU)
#define | USB_FADDR_UPDATE (0x1U << 7)
#define | USB_POWER_SUSEN (0x1U << 0)
#define | USB_POWER_SUSMD (0x1U << 1)
#define | USB_POWER_RESUME (0x1U << 2)
#define | USB_POWER_USBRST (0x1U << 3)
#define | USB_POWER_ISOUD (0x1U << 7)
#define | USB_INTRIN_EP0 (0x1U << 0)
#define | USB_INTRIN_IN1 (0x1U << 1)
#define | USB_INTRIN_IN2 (0x1U << 2)
#define | USB_INTRIN_IN3 (0x1U << 3)
#define | USB_INTROUT_OUT1 (0x1U << 1)
#define | USB_INTROUT_OUT2 (0x1U << 2)
#define | USB_INTROUT_OUT3 (0x1U << 3)
#define | USB_INTRUSB_SUSIS (0x1U << 0)
#define | USB_INTRUSB_RSUIS (0x1U << 1)
#define | USB_INTRUSB_RSTIS (0x1U << 2)
#define | USB_INTRUSB_SOFIS (0x1U << 3)
#define | USB_INTRINE_EP0E (0x1U << 0)
#define | USB_INTRINE_IN1E (0x1U << 1)
#define | USB_INTRINE_IN2E (0x1U << 2)
#define | USB_INTRINE_IN3E (0x1U << 3)
#define | USB_INTROUTE_OUT1E (0x1U << 1)
#define | USB_INTROUTE_OUT2E (0x1U << 2)
#define | USB_INTROUTE_OUT3E (0x1U << 3)
#define | USB_INTRUSBE_SUSIE (0x1U << 0)
#define | USB_INTRUSBE_RSUIE (0x1U << 1)
#define | USB_INTRUSBE_RSTIE (0x1U << 2)
#define | USB_INTRUSBE_SOFIE (0x1U << 3)
#define | USB_CSR0_OUTPKTRDY (0x1U << 0)
#define | USB_CSR0_INPKTRDY (0x1U << 1)
#define | USB_CSR0_SENTSTALL (0x1U << 2)
#define | USB_CSR0_DATAEND (0x1U << 3)
#define | USB_CSR0_SETUPEND (0x1U << 4)
#define | USB_CSR0_SENDSTALL (0x1U << 5)
#define | USB_CSR0_SVDOUTPKTRDY (0x1U << 6)
#define | USB_CSR0_SVDSETUPEND (0x1U << 7)
#define | USB_INCSR1_INPKTRDY (0x1U << 0)
#define | USB_INCSR1_FIFONE (0x1U << 1)
#define | USB_INCSR1_UNDERRUN (0x1U << 2)
#define | USB_INCSR1_FLUSHFIFO (0x1U << 3)
#define | USB_INCSR1_SENDSTALL (0x1U << 4)
#define | USB_INCSR1_SENTSTALL (0x1U << 5)
#define | USB_INCSR1_CLRDATATOG (0x1U << 6)
#define | USB_INCSR2_FRCDATATOG (0x1U << 3)
#define | USB_INCSR2_DMAEN (0x1U << 4)
#define | USB_INCSR2_DIRSEL (0x1U << 5)
#define | USB_INCSR2_ISO (0x1U << 6)
#define | USB_INCSR2_AUTOSET (0x1U << 7)
#define | USB_OUTCSR1_OUTPKTRDY (0x1U << 0)
#define | USB_OUTCSR1_FIFOFULL (0x1U << 1)
#define | USB_OUTCSR1_OVERRUN (0x1U << 2)
#define | USB_OUTCSR1_DATAERROR (0x1U << 3)
#define | USB_OUTCSR1_FLUSHFIFO (0x1U << 4)
#define | USB_OUTCSR1_SENDSTALL (0x1U << 5)
#define | USB_OUTCSR1_SENTSTALL (0x1U << 6)
#define | USB_OUTCSR1_CLRDATATOG (0x1U << 7)
#define | USB_OUTCSR2_DMAMODE (0x1U << 4)
#define | USB_OUTCSR2_DMAEN (0x1U << 5)
#define | USB_OUTCSR2_ISO (0x1U << 6)
#define | USB_OUTCSR2_AUTOCLR (0x1U << 7)
#define | TIM_CR1_CEN (0x1U << 0)
#define | TIM_CR1_UDIS (0x1U << 1)
#define | TIM_CR1_URS (0x1U << 2)
#define | TIM_CR1_OPM (0x1U << 3)
#define | TIM_CR1_DIR (0x1U << 4)
#define | TIM_CR1_CMS (0x3U << 5)
#define | TIM_CR1_CMS_0 (0x1U << 5)
#define | TIM_CR1_CMS_1 (0x1U << 6)
#define | TIM_CR1_ARPE (0x1U << 7)
#define | TIM_CR1_CKD (0x3U << 8)
#define | TIM_CR1_CKD_0 (0x1U << 8)
#define | TIM_CR1_CKD_1 (0x1U << 9)
#define | TIM_CR2_CCPC (0x1U << 0)
#define | TIM_CR2_CCUS (0x1U << 2)
#define | TIM_CR2_CCDS (0x1U << 3)
#define | TIM_CR2_MMS (0x7U << 4)
#define | TIM_CR2_MMS_0 (0x1U << 4)
#define | TIM_CR2_MMS_1 (0x1U << 5)
#define | TIM_CR2_MMS_2 (0x1U << 6)
#define | TIM_CR2_TI1S (0x1U << 7)
#define | TIM_CR2_OIS1 (0x1U << 8)
#define | TIM_CR2_OIS1N (0x1U << 9)
#define | TIM_CR2_OIS2 (0x1U << 10)
#define | TIM_CR2_OIS2N (0x1U << 11)
#define | TIM_CR2_OIS3 (0x1U << 12)
#define | TIM_CR2_OIS3N (0x1U << 13)
#define | TIM_CR2_OIS4 (0x1U << 14)
#define | TIM_SMCR_SMS (0x7U << 0)
#define | TIM_SMCR_SMS_0 (0x1U << 0)
#define | TIM_SMCR_SMS_1 (0x1U << 1)
#define | TIM_SMCR_SMS_2 (0x1U << 2)
#define | TIM_SMCR_TS (0x7U << 4)
#define | TIM_SMCR_TS_0 (0x1U << 4)
#define | TIM_SMCR_TS_1 (0x1U << 5)
#define | TIM_SMCR_TS_2 (0x1U << 6)
#define | TIM_SMCR_MSM (0x1U << 7)
#define | TIM_SMCR_ETF (0xFU << 8)
#define | TIM_SMCR_ETF_0 (0x1U << 8)
#define | TIM_SMCR_ETF_1 (0x1U << 9)
#define | TIM_SMCR_ETF_2 (0x1U << 10)
#define | TIM_SMCR_ETF_3 (0x1U << 11)
#define | TIM_SMCR_ETPS (0x3U << 12)
#define | TIM_SMCR_ETPS_0 (0x1U << 12)
#define | TIM_SMCR_ETPS_1 (0x1U << 13)
#define | TIM_SMCR_ECE (0x1U << 14)
#define | TIM_SMCR_ETP (0x1U << 15)
#define | TIM_DIER_UIE (0x1U << 0)
#define | TIM_DIER_CC1IE (0x1U << 1)
#define | TIM_DIER_CC2IE (0x1U << 2)
#define | TIM_DIER_CC3IE (0x1U << 3)
#define | TIM_DIER_CC4IE (0x1U << 4)
#define | TIM_DIER_COMIE (0x1U << 5)
#define | TIM_DIER_TIE (0x1U << 6)
#define | TIM_DIER_BIE (0x1U << 7)
#define | TIM_DIER_UDE (0x1U << 8)
#define | TIM_DIER_CC1DE (0x1U << 9)
#define | TIM_DIER_CC2DE (0x1U << 10)
#define | TIM_DIER_CC3DE (0x1U << 11)
#define | TIM_DIER_CC4DE (0x1U << 12)
#define | TIM_DIER_COMDE (0x1U << 13)
#define | TIM_DIER_TDE (0x1U << 14)
#define | TIM_SR_UIF (0x1U << 0)
#define | TIM_SR_CC1IF (0x1U << 1)
#define | TIM_SR_CC2IF (0x1U << 2)
#define | TIM_SR_CC3IF (0x1U << 3)
#define | TIM_SR_CC4IF (0x1U << 4)
#define | TIM_SR_COMIF (0x1U << 5)
#define | TIM_SR_TIF (0x1U << 6)
#define | TIM_SR_BIF (0x1U << 7)
#define | TIM_SR_CC1OF (0x1U << 9)
#define | TIM_SR_CC2OF (0x1U << 10)
#define | TIM_SR_CC3OF (0x1U << 11)
#define | TIM_SR_CC4OF (0x1U << 12)
#define | TIM_EGR_UG (0x1U << 0)
#define | TIM_EGR_CC1G (0x1U << 1)
#define | TIM_EGR_CC2G (0x1U << 2)
#define | TIM_EGR_CC3G (0x1U << 3)
#define | TIM_EGR_CC4G (0x1U << 4)
#define | TIM_EGR_COMG (0x1U << 5)
#define | TIM_EGR_TG (0x1U << 6)
#define | TIM_EGR_BG (0x1U << 7)
#define | TIM_CCMR1_CC1S (0x3U << 0)
#define | TIM_CCMR1_CC1S_0 (0x1U << 0)
#define | TIM_CCMR1_CC1S_1 (0x1U << 1)
#define | TIM_CCMR1_OC1FE (0x1U << 2)
#define | TIM_CCMR1_OC1PE (0x1U << 3)
#define | TIM_CCMR1_OC1M (0x7U << 4)
#define | TIM_CCMR1_OC1M_0 (0x1U << 4)
#define | TIM_CCMR1_OC1M_1 (0x1U << 5)
#define | TIM_CCMR1_OC1M_2 (0x1U << 6)
#define | TIM_CCMR1_OC1CE (0x1U << 7)
#define | TIM_CCMR1_CC2S (0x3U << 8)
#define | TIM_CCMR1_CC2S_0 (0x1U << 8)
#define | TIM_CCMR1_CC2S_1 (0x1U << 9)
#define | TIM_CCMR1_OC2FE (0x1U << 10)
#define | TIM_CCMR1_OC2PE (0x1U << 11)
#define | TIM_CCMR1_OC2M (0x7U << 12)
#define | TIM_CCMR1_OC2M_0 (0x1U << 12)
#define | TIM_CCMR1_OC2M_1 (0x1U << 13)
#define | TIM_CCMR1_OC2M_2 (0x1U << 14)
#define | TIM_CCMR1_OC2CE (0x1U << 15)
#define | TIM_CCMR1_IC1PSC (0x3U << 2)
#define | TIM_CCMR1_IC1PSC_0 (0x1U << 2)
#define | TIM_CCMR1_IC1PSC_1 (0x1U << 3)
#define | TIM_CCMR1_IC1F (0xFU << 4)
#define | TIM_CCMR1_IC1F_0 (0x1U << 4)
#define | TIM_CCMR1_IC1F_1 (0x1U << 5)
#define | TIM_CCMR1_IC1F_2 (0x1U << 6)
#define | TIM_CCMR1_IC1F_3 (0x1U << 7)
#define | TIM_CCMR1_IC2PSC (0x3U << 10)
#define | TIM_CCMR1_IC2PSC_0 (0x1U << 10)
#define | TIM_CCMR1_IC2PSC_1 (0x1U << 11)
#define | TIM_CCMR1_IC2F (0xFU << 12)
#define | TIM_CCMR1_IC2F_0 (0x1U << 12)
#define | TIM_CCMR1_IC2F_1 (0x1U << 13)
#define | TIM_CCMR1_IC2F_2 (0x1U << 14)
#define | TIM_CCMR1_IC2F_3 (0x1U << 15)
#define | TIM_CCMR2_CC3S (0x3U << 0)
#define | TIM_CCMR2_CC3S_0 (0x1U << 0)
#define | TIM_CCMR2_CC3S_1 (0x1U << 1)
#define | TIM_CCMR2_OC3FE (0x1U << 2)
#define | TIM_CCMR2_OC3PE (0x1U << 3)
#define | TIM_CCMR2_OC3M (0x7U << 4)
#define | TIM_CCMR2_OC3M_0 (0x1U << 4)
#define | TIM_CCMR2_OC3M_1 (0x1U << 5)
#define | TIM_CCMR2_OC3M_2 (0x1U << 6)
#define | TIM_CCMR2_OC3CE (0x1U << 7)
#define | TIM_CCMR2_CC4S (0x3U << 8)
#define | TIM_CCMR2_CC4S_0 (0x1U << 8)
#define | TIM_CCMR2_CC4S_1 (0x1U << 9)
#define | TIM_CCMR2_OC4FE (0x1U << 10)
#define | TIM_CCMR2_OC4PE (0x1U << 11)
#define | TIM_CCMR2_OC4M (0x7U << 12)
#define | TIM_CCMR2_OC4M_0 (0x1U << 12)
#define | TIM_CCMR2_OC4M_1 (0x1U << 13)
#define | TIM_CCMR2_OC4M_2 (0x1U << 14)
#define | TIM_CCMR2_OC4CE (0x1U << 15)
#define | TIM_CCMR2_IC3PSC (0x3U << 2)
#define | TIM_CCMR2_IC3PSC_0 (0x1U << 2)
#define | TIM_CCMR2_IC3PSC_1 (0x1U << 3)
#define | TIM_CCMR2_IC3F (0xFU << 4)
#define | TIM_CCMR2_IC3F_0 (0x1U << 4)
#define | TIM_CCMR2_IC3F_1 (0x1U << 5)
#define | TIM_CCMR2_IC3F_2 (0x1U << 6)
#define | TIM_CCMR2_IC3F_3 (0x1U << 7)
#define | TIM_CCMR2_IC4PSC (0x3U << 10)
#define | TIM_CCMR2_IC4PSC_0 (0x1U << 10)
#define | TIM_CCMR2_IC4PSC_1 (0x1U << 11)
#define | TIM_CCMR2_IC4F (0xFU << 12)
#define | TIM_CCMR2_IC4F_0 (0x1U << 12)
#define | TIM_CCMR2_IC4F_1 (0x1U << 13)
#define | TIM_CCMR2_IC4F_2 (0x1U << 14)
#define | TIM_CCMR2_IC4F_3 (0x1U << 15)
#define | TIM_CCER_CC1E (0x1U << 0)
#define | TIM_CCER_CC1P (0x1U << 1)
#define | TIM_CCER_CC1NE (0x1U << 2)
#define | TIM_CCER_CC1NP (0x1U << 3)
#define | TIM_CCER_CC2E (0x1U << 4)
#define | TIM_CCER_CC2P (0x1U << 5)
#define | TIM_CCER_CC2NE (0x1U << 6)
#define | TIM_CCER_CC2NP (0x1U << 7)
#define | TIM_CCER_CC3E (0x1U << 8)
#define | TIM_CCER_CC3P (0x1U << 9)
#define | TIM_CCER_CC3NE (0x1U << 10)
#define | TIM_CCER_CC3NP (0x1U << 11)
#define | TIM_CCER_CC4E (0x1U << 12)
#define | TIM_CCER_CC4P (0x1U << 13)
#define | TIM_CNT_CNT (0xFFFFFU)
#define | TIM_PSC_PSC (0xFFFFU)
#define | TIM_ARR_ARR (0xFFFFFU)
#define | TIM_RCR_REP (0xFFU)
#define | TIM_CCR1_CCR1 (0xFFFFFU)
#define | TIM_CCR2_CCR2 (0xFFFFFU)
#define | TIM_CCR3_CCR3 (0xFFFFFU)
#define | TIM_CCR4_CCR4 (0xFFFFFU)
#define | TIM_BDTR_DTG (0xFFU << 0)
#define | TIM_BDTR_DTG_0 (0x1U << 0)
#define | TIM_BDTR_DTG_1 (0x1U << 1)
#define | TIM_BDTR_DTG_2 (0x1U << 2)
#define | TIM_BDTR_DTG_3 (0x1U << 3)
#define | TIM_BDTR_DTG_4 (0x1U << 4)
#define | TIM_BDTR_DTG_5 (0x1U << 5)
#define | TIM_BDTR_DTG_6 (0x1U << 6)
#define | TIM_BDTR_DTG_7 (0x1U << 7)
#define | TIM_BDTR_LOCK (0x3U << 8)
#define | TIM_BDTR_LOCK_0 (0x1U << 8)
#define | TIM_BDTR_LOCK_1 (0x1U << 9)
#define | TIM_BDTR_OSSI (0x1U << 10)
#define | TIM_BDTR_OSSR (0x1U << 11)
#define | TIM_BDTR_BKE (0x1U << 12)
#define | TIM_BDTR_BKP (0x1U << 13)
#define | TIM_BDTR_AOE (0x1U << 14)
#define | TIM_BDTR_MOE (0x1U << 15)
#define | EXTI_IMR_MR0 ((uint32_t)0x00000001)
#define | EXTI_IMR_MR1 ((uint32_t)0x00000002)
#define | EXTI_IMR_MR2 ((uint32_t)0x00000004)
#define | EXTI_IMR_MR3 ((uint32_t)0x00000008)
#define | EXTI_IMR_MR4 ((uint32_t)0x00000010)
#define | EXTI_IMR_MR5 ((uint32_t)0x00000020)
#define | EXTI_IMR_MR6 ((uint32_t)0x00000040)
#define | EXTI_IMR_MR7 ((uint32_t)0x00000080)
#define | EXTI_IMR_MR8 ((uint32_t)0x00000100)
#define | EXTI_IMR_MR9 ((uint32_t)0x00000200)
#define | EXTI_IMR_MR10 ((uint32_t)0x00000400)
#define | EXTI_IMR_MR11 ((uint32_t)0x00000800)
#define | EXTI_IMR_MR12 ((uint32_t)0x00001000)
#define | EXTI_IMR_MR13 ((uint32_t)0x00002000)
#define | EXTI_IMR_MR14 ((uint32_t)0x00004000)
#define | EXTI_IMR_MR15 ((uint32_t)0x00008000)
#define | EXTI_IMR_MR16 ((uint32_t)0x00010000)
#define | EXTI_IMR_MR17 ((uint32_t)0x00020000)
#define | EXTI_IMR_MR18 ((uint32_t)0x00040000)
#define | EXTI_EMR_MR0 ((uint32_t)0x00000001)
#define | EXTI_EMR_MR1 ((uint32_t)0x00000002)
#define | EXTI_EMR_MR2 ((uint32_t)0x00000004)
#define | EXTI_EMR_MR3 ((uint32_t)0x00000008)
#define | EXTI_EMR_MR4 ((uint32_t)0x00000010)
#define | EXTI_EMR_MR5 ((uint32_t)0x00000020)
#define | EXTI_EMR_MR6 ((uint32_t)0x00000040)
#define | EXTI_EMR_MR7 ((uint32_t)0x00000080)
#define | EXTI_EMR_MR8 ((uint32_t)0x00000100)
#define | EXTI_EMR_MR9 ((uint32_t)0x00000200)
#define | EXTI_EMR_MR10 ((uint32_t)0x00000400)
#define | EXTI_EMR_MR11 ((uint32_t)0x00000800)
#define | EXTI_EMR_MR12 ((uint32_t)0x00001000)
#define | EXTI_EMR_MR13 ((uint32_t)0x00002000)
#define | EXTI_EMR_MR14 ((uint32_t)0x00004000)
#define | EXTI_EMR_MR15 ((uint32_t)0x00008000)
#define | EXTI_EMR_MR16 ((uint32_t)0x00010000)
#define | EXTI_EMR_MR17 ((uint32_t)0x00020000)
#define | EXTI_EMR_MR18 ((uint32_t)0x00040000)
#define | EXTI_RTSR_TR0 ((uint32_t)0x00000001)
#define | EXTI_RTSR_TR1 ((uint32_t)0x00000002)
#define | EXTI_RTSR_TR2 ((uint32_t)0x00000004)
#define | EXTI_RTSR_TR3 ((uint32_t)0x00000008)
#define | EXTI_RTSR_TR4 ((uint32_t)0x00000010)
#define | EXTI_RTSR_TR5 ((uint32_t)0x00000020)
#define | EXTI_RTSR_TR6 ((uint32_t)0x00000040)
#define | EXTI_RTSR_TR7 ((uint32_t)0x00000080)
#define | EXTI_RTSR_TR8 ((uint32_t)0x00000100)
#define | EXTI_RTSR_TR9 ((uint32_t)0x00000200)
#define | EXTI_RTSR_TR10 ((uint32_t)0x00000400)
#define | EXTI_RTSR_TR11 ((uint32_t)0x00000800)
#define | EXTI_RTSR_TR12 ((uint32_t)0x00001000)
#define | EXTI_RTSR_TR13 ((uint32_t)0x00002000)
#define | EXTI_RTSR_TR14 ((uint32_t)0x00004000)
#define | EXTI_RTSR_TR15 ((uint32_t)0x00008000)
#define | EXTI_RTSR_TR16 ((uint32_t)0x00010000)
#define | EXTI_RTSR_TR17 ((uint32_t)0x00020000)
#define | EXTI_RTSR_TR18 ((uint32_t)0x00040000)
#define | EXTI_FTSR_TR0 ((uint32_t)0x00000001)
#define | EXTI_FTSR_TR1 ((uint32_t)0x00000002)
#define | EXTI_FTSR_TR2 ((uint32_t)0x00000004)
#define | EXTI_FTSR_TR3 ((uint32_t)0x00000008)
#define | EXTI_FTSR_TR4 ((uint32_t)0x00000010)
#define | EXTI_FTSR_TR5 ((uint32_t)0x00000020)
#define | EXTI_FTSR_TR6 ((uint32_t)0x00000040)
#define | EXTI_FTSR_TR7 ((uint32_t)0x00000080)
#define | EXTI_FTSR_TR8 ((uint32_t)0x00000100)
#define | EXTI_FTSR_TR9 ((uint32_t)0x00000200)
#define | EXTI_FTSR_TR10 ((uint32_t)0x00000400)
#define | EXTI_FTSR_TR11 ((uint32_t)0x00000800)
#define | EXTI_FTSR_TR12 ((uint32_t)0x00001000)
#define | EXTI_FTSR_TR13 ((uint32_t)0x00002000)
#define | EXTI_FTSR_TR14 ((uint32_t)0x00004000)
#define | EXTI_FTSR_TR15 ((uint32_t)0x00008000)
#define | EXTI_FTSR_TR16 ((uint32_t)0x00010000)
#define | EXTI_FTSR_TR17 ((uint32_t)0x00020000)
#define | EXTI_FTSR_TR18 ((uint32_t)0x00040000)
#define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
#define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
#define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
#define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
#define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
#define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
#define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
#define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
#define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
#define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
#define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
#define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
#define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
#define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
#define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
#define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
#define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
#define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
#define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
#define | EXTI_PR_PR0 ((uint32_t)0x00000001)
#define | EXTI_PR_PR1 ((uint32_t)0x00000002)
#define | EXTI_PR_PR2 ((uint32_t)0x00000004)
#define | EXTI_PR_PR3 ((uint32_t)0x00000008)
#define | EXTI_PR_PR4 ((uint32_t)0x00000010)
#define | EXTI_PR_PR5 ((uint32_t)0x00000020)
#define | EXTI_PR_PR6 ((uint32_t)0x00000040)
#define | EXTI_PR_PR7 ((uint32_t)0x00000080)
#define | EXTI_PR_PR8 ((uint32_t)0x00000100)
#define | EXTI_PR_PR9 ((uint32_t)0x00000200)
#define | EXTI_PR_PR10 ((uint32_t)0x00000400)
#define | EXTI_PR_PR11 ((uint32_t)0x00000800)
#define | EXTI_PR_PR12 ((uint32_t)0x00001000)
#define | EXTI_PR_PR13 ((uint32_t)0x00002000)
#define | EXTI_PR_PR14 ((uint32_t)0x00004000)
#define | EXTI_PR_PR15 ((uint32_t)0x00008000)
#define | EXTI_PR_PR16 ((uint32_t)0x00010000)
#define | EXTI_PR_PR17 ((uint32_t)0x00020000)
#define | EXTI_PR_PR18 ((uint32_t)0x00040000)
#define | AFIO_EXTICR1_EXTI0_Msk ((uint16_t)0x000F)
#define | AFIO_EXTICR1_EXTI1_Msk ((uint16_t)0x00F0)
#define | AFIO_EXTICR1_EXTI2_Msk ((uint16_t)0x0F00)
#define | AFIO_EXTICR1_EXTI3_Msk ((uint16_t)0xF000)
#define | AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
#define | AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
#define | AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
#define | AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR2_EXTI4_Msk ((uint16_t)0x000F)
#define | AFIO_EXTICR2_EXTI5_Msk ((uint16_t)0x00F0)
#define | AFIO_EXTICR2_EXTI6_Msk ((uint16_t)0x0F00)
#define | AFIO_EXTICR2_EXTI7_Msk ((uint16_t)0xF000)
#define | AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR3_EXTI8_Msk ((uint16_t)0x000F)
#define | AFIO_EXTICR3_EXTI9_Msk ((uint16_t)0x00F0)
#define | AFIO_EXTICR3_EXTI10_Msk ((uint16_t)0x0F00)
#define | AFIO_EXTICR3_EXTI11_Msk ((uint16_t)0xF000)
#define | AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
#define | AFIO_EXTICR4_EXTI12_Msk ((uint16_t)0x000F)
#define | AFIO_EXTICR4_EXTI13_Msk ((uint16_t)0x00F0)
#define | AFIO_EXTICR4_EXTI14_Msk ((uint16_t)0x0F00)
#define | AFIO_EXTICR4_EXTI15_Msk ((uint16_t)0xF000)
#define | AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
#define | AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
#define | AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
#define | AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
#define | AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
#define | AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
#define | AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
#define | AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
#define | AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
#define | RTC_CRH_SECIE ((uint8_t)0x01)
#define | RTC_CRH_ALRIE ((uint8_t)0x02)
#define | RTC_CRH_OWIE ((uint8_t)0x04)
#define | RTC_CRL_SECF ((uint8_t)0x01)
#define | RTC_CRL_ALRF ((uint8_t)0x02)
#define | RTC_CRL_OWF ((uint8_t)0x04)
#define | RTC_CRL_RSF ((uint8_t)0x08)
#define | RTC_CRL_CNF ((uint8_t)0x10)
#define | RTC_CRL_RTOFF ((uint8_t)0x20)
#define | RTC_PRLH_PRL ((uint16_t)0x000F)
#define | RTC_PRLL_PRL ((uint16_t)0xFFFF)
#define | RTC_DIVH_RTC_DIV ((uint16_t)0x000F)
#define | RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)
#define | RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)
#define | RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)
#define | RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)
#define | RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)
#define | BKP_RTCCR_CAL ((uint16_t)0x007F)
#define | BKP_RTCCR_CCO ((uint16_t)0x0080)
#define | BKP_RTCCR_ASOE ((uint16_t)0x0100)
#define | BKP_RTCCR_ASOS ((uint16_t)0x0200)
#define | BKP_CR_TPE ((uint8_t)0x01)
#define | BKP_CR_TPAL ((uint8_t)0x02)
#define | BKP_CSR_CTE ((uint16_t)0x0001)
#define | BKP_CSR_CTI ((uint16_t)0x0002)
#define | BKP_CSR_TPIE ((uint16_t)0x0004)
#define | BKP_CSR_TEF ((uint16_t)0x0100)
#define | BKP_CSR_TIF ((uint16_t)0x0200)
#define | WWDG_CR_T ((uint8_t)0x7F)
#define | WWDG_CR_T0 ((uint8_t)0x01)
#define | WWDG_CR_T1 ((uint8_t)0x02)
#define | WWDG_CR_T2 ((uint8_t)0x04)
#define | WWDG_CR_T3 ((uint8_t)0x08)
#define | WWDG_CR_T4 ((uint8_t)0x10)
#define | WWDG_CR_T5 ((uint8_t)0x20)
#define | WWDG_CR_T6 ((uint8_t)0x40)
#define | WWDG_CR_WDGA ((uint8_t)0x80)
#define | WWDG_CFR_W ((uint16_t)0x007F)
#define | WWDG_CFR_W0 ((uint16_t)0x0001)
#define | WWDG_CFR_W1 ((uint16_t)0x0002)
#define | WWDG_CFR_W2 ((uint16_t)0x0004)
#define | WWDG_CFR_W3 ((uint16_t)0x0008)
#define | WWDG_CFR_W4 ((uint16_t)0x0010)
#define | WWDG_CFR_W5 ((uint16_t)0x0020)
#define | WWDG_CFR_W6 ((uint16_t)0x0040)
#define | WWDG_CFR_WDGTB ((uint16_t)0x0180)
#define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
#define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
#define | WWDG_CFR_EWI ((uint16_t)0x0200)
#define | WWDG_SR_EWIF ((uint8_t)0x01)
#define | IWDG_KR_KEY ((uint16_t)0xFFFF)
#define | IWDG_PR_PR ((uint8_t)0x07)
#define | IWDG_PR_PR_0 ((uint8_t)0x01)
#define | IWDG_PR_PR_1 ((uint8_t)0x02)
#define | IWDG_PR_PR_2 ((uint8_t)0x04)
#define | IWDG_RLR_RL ((uint16_t)0x0FFF)
#define | IWDG_SR_PVU ((uint8_t)0x01)
#define | IWDG_SR_RVU ((uint8_t)0x02)
#define | ADC_SR_AWD ((uint8_t)0x01)
#define | ADC_SR_EOC ((uint8_t)0x02)
#define | ADC_SR_JEOC ((uint8_t)0x04)
#define | ADC_SR_JSTRT ((uint8_t)0x08)
#define | ADC_SR_STRT ((uint8_t)0x10)
#define | ADC_SR_EMP ((uint8_t)0x20)
#define | ADC_SR_OVF ((uint8_t)0x40)
#define | ADC_CR1_AWDCH ((uint32_t)0x0000001F)
#define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
#define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
#define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
#define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
#define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
#define | ADC_CR1_EOCIE ((uint32_t)0x00000020)
#define | ADC_CR1_AWDIE ((uint32_t)0x00000040)
#define | ADC_CR1_JEOCIE ((uint32_t)0x00000080)
#define | ADC_CR1_SCAN ((uint32_t)0x00000100)
#define | ADC_CR1_AWDSGL ((uint32_t)0x00000200)
#define | ADC_CR1_JAUTO ((uint32_t)0x00000400)
#define | ADC_CR1_DISCEN ((uint32_t)0x00000800)
#define | ADC_CR1_JDISCEN ((uint32_t)0x00001000)
#define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
#define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
#define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
#define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
#define | ADC_CR1_JAWDEN ((uint32_t)0x00400000)
#define | ADC_CR1_AWDEN ((uint32_t)0x00800000)
#define | ADC_CR2_ADON ((uint32_t)0x00000001)
#define | ADC_CR2_CONT ((uint32_t)0x00000002)
#define | ADC_CR2_CAL ((uint32_t)0x00000004)
#define | ADC_CR2_RSTCAL ((uint32_t)0x00000008)
#define | ADC_CR2_DMAEN ((uint32_t)0x00000100)
#define | ADC_CR2_JDMAEN ((uint32_t)0x00000200)
#define | ADC_CR2_JEXTSYNC ((uint32_t)0x00000400)
#define | ADC_CR2_ALIGN ((uint32_t)0x00000800)
#define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000)
#define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)
#define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)
#define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)
#define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)
#define | ADC_CR2_EXTSYNC ((uint32_t)0x00010000)
#define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000)
#define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)
#define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)
#define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)
#define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000)
#define | ADC_CR2_JSWSTART ((uint32_t)0x00200000)
#define | ADC_CR2_SWSTART ((uint32_t)0x00400000)
#define | ADC_CR2_TSVREFE ((uint32_t)0x00800000)
#define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
#define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
#define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
#define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
#define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
#define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
#define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
#define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
#define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
#define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
#define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
#define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
#define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
#define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
#define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
#define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
#define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
#define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
#define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
#define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
#define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
#define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
#define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
#define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
#define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
#define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
#define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
#define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
#define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
#define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
#define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
#define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
#define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
#define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
#define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
#define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
#define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
#define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
#define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
#define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
#define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
#define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
#define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
#define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
#define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
#define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
#define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
#define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
#define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
#define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
#define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
#define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
#define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
#define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
#define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
#define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
#define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
#define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
#define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
#define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
#define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
#define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
#define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
#define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
#define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
#define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
#define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
#define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
#define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
#define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
#define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
#define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
#define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
#define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
#define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
#define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
#define | ADC_HTR_HT ((uint16_t)0x0FFF)
#define | ADC_LTR_LT ((uint16_t)0x0FFF)
#define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
#define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
#define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
#define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
#define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
#define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
#define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
#define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
#define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
#define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
#define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
#define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
#define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
#define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
#define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
#define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
#define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
#define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
#define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
#define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
#define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
#define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
#define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
#define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
#define | ADC_SQR1_L ((uint32_t)0x00F00000)
#define | ADC_SQR1_L_0 ((uint32_t)0x00100000)
#define | ADC_SQR1_L_1 ((uint32_t)0x00200000)
#define | ADC_SQR1_L_2 ((uint32_t)0x00400000)
#define | ADC_SQR1_L_3 ((uint32_t)0x00800000)
#define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
#define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
#define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
#define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
#define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
#define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
#define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
#define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
#define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
#define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
#define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
#define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
#define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
#define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
#define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
#define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
#define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
#define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
#define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
#define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
#define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
#define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
#define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
#define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
#define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
#define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
#define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
#define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
#define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
#define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
#define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
#define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
#define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
#define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
#define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
#define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
#define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
#define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
#define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
#define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
#define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
#define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
#define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
#define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
#define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
#define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
#define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
#define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
#define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
#define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
#define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
#define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
#define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
#define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
#define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
#define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
#define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
#define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
#define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
#define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
#define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
#define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
#define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
#define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
#define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
#define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
#define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
#define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
#define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
#define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
#define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
#define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
#define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
#define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
#define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
#define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
#define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
#define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
#define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
#define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
#define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
#define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
#define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
#define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
#define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
#define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
#define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
#define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
#define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
#define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
#define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
#define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
#define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
#define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
#define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
#define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
#define | ADC_JSQR_JL ((uint32_t)0x00300000)
#define | ADC_JSQR_JL_0 ((uint32_t)0x00100000)
#define | ADC_JSQR_JL_1 ((uint32_t)0x00200000)
#define | ADC_JDR1_JDATA ((uint16_t)0xFFFF)
#define | ADC_JDR2_JDATA ((uint16_t)0xFFFF)
#define | ADC_JDR3_JDATA ((uint16_t)0xFFFF)
#define | ADC_JDR4_JDATA ((uint16_t)0xFFFF)
#define | ADC_DR_DATA ((uint32_t)0x0000FFFF)
#define | ADC_CR3_ADVMODE ((uint32_t)0x00000003)
#define | ADC_CR3_SAMCHN ((uint32_t)0x0000000C)
#define | ADC_CR3_VREFCFG ((uint32_t)0x00000030)
#define | ADC_CR3_12BIT ((uint32_t)0x00000040)
#define | ADC_CR3_PRS ((uint32_t)0x0000FF00)
#define | ADC_CR3_OVFIE ((uint32_t)0x00010000)
#define | ADC_CR3_EMPIE ((uint32_t)0x00020000)
#define | ADC_JDMAR_JDATA ((uint16_t)0xFFFF)
#define | ISO_FIFOSR_FULL (0x1U << 0)
#define | ISO_FIFOSR_EMPTY (0x1U << 1)
#define | CACHE_CR_LATENCY_Msk (0xFU)
#define | CACHE_CR_LATENCY_0WS (0x0U)
#define | CACHE_CR_LATENCY_1WS (0x1U)
#define | CACHE_CR_LATENCY_2WS (0x2U)
#define | CACHE_CR_LATENCY_3WS (0x3U)
#define | CACHE_CR_LATENCY_4WS (0x4U)
#define | CACHE_CR_LATENCY_5WS (0x5U)
#define | CACHE_CR_LATENCY_6WS (0x6U)
#define | CACHE_CR_LATENCY_7WS (0x7U)
#define | CACHE_CR_LATENCY_8WS (0x8U)
#define | CACHE_CR_LATENCY_9WS (0x9U)
#define | CACHE_CR_LATENCY_10WS (0xAU)
#define | CACHE_CR_LATENCY_11WS (0xBU)
#define | CACHE_CR_LATENCY_12WS (0xCU)
#define | CACHE_CR_LATENCY_13WS (0xDU)
#define | CACHE_CR_LATENCY_14WS (0xEU)
#define | CACHE_CR_LATENCY_15WS (0xFU)
#define | CACHE_CR_PREFEN_Msk (0x3U << 4)
#define | CACHE_CR_PREFEN_OFF (0x0U << 4)
#define | CACHE_CR_PREFEN_ON (0x1U << 4)
#define | CACHE_CR_HIFREQ (0x1U << 8)
#define | CACHE_CR_CHEEN (0x3U << 24)
#define | FMC_CON_OP_Msk (0x1FU)
#define | FMC_CON_WREN (0x1U << 6)
#define | FMC_CON_WR (0x1U << 7)
#define | FMC_CON_SETHLDCNT_Msk (0x7FU << 8)
#define | FMC_CRCON_CRCEN (0x1U << 0)
#define | FMC_CRCON_CRCF (0x1U << 1)
#define | FMC_CRCON_PAUSE (0x1U << 2)
#define | FMC_CRCON_SLOWRD (0x1U << 3)
#define | FMC_CRCON_CRCFIE (0x1U << 8)
#define | FMC_CRCON_PERIOD_Pos (12U)
#define | FMC_CRCON_PERIOD_Msk (0xFU << FMC_CRCON_PERIOD_Pos)
#define | FMC_CRCON_CRCLEN_Pos (16U)
#define | FMC_CRCON_CRCLEN_Msk (0x3FFU << FMC_CRCON_CRCLEN_Pos)
#define | FMC_STAT_ERR (0x1U << 2)
#define | ANCTL_BGCR2_TEMPOUTEN (0x1U << 1)
#define | ANCTL_MHSIENR_MHSION (0x1U << 0)
#define | ANCTL_MHSISR_MHSIRDY (0x1U << 0)
#define | ANCTL_FHSIENR_FHSION (0x1U << 0)
#define | ANCTL_FHSISR_FHSIRDY (0x1U << 0)
#define | ANCTL_LSIENR_LSION (0x1U << 0)
#define | ANCTL_LSISR_LSIRDY (0x1U << 0)
#define | ANCTL_HSECR0_HSEON (0x1U << 0)
#define | ANCTL_HSECR0_BYPASS (0x1U << 1)
#define | ANCTL_HSECR1_PADOEN (0x1U << 1)
#define | ANCTL_HSESR_HSERDY (0x1U << 0)
#define | ANCTL_PLLCR_PLLMUL_Msk (0x3U << 6)
#define | ANCTL_PLLCR_PLLMUL_24 (0x0U << 6)
#define | ANCTL_PLLCR_PLLMUL_20 (0x1U << 6)
#define | ANCTL_PLLCR_PLLMUL_16 (0x2U << 6)
#define | ANCTL_PLLCR_PLLMUL_12 (0x3U << 6)
#define | ANCTL_PLLENR_PLLON (0x1U << 0)
#define | ANCTL_PLLSR_PLLRDY_Msk (0x3U)
#define | ANCTL_PVDCR_PLS_Msk (0x7U)
#define | ANCTL_PVDCR_PLS_LEV0 (0x0U)
#define | ANCTL_PVDCR_PLS_LEV1 (0x1U)
#define | ANCTL_PVDCR_PLS_LEV2 (0x2U)
#define | ANCTL_PVDCR_PLS_LEV3 (0x3U)
#define | ANCTL_PVDCR_PLS_LEV4 (0x4U)
#define | ANCTL_PVDCR_PLS_LEV5 (0x5U)
#define | ANCTL_PVDCR_PLS_LEV6 (0x6U)
#define | ANCTL_PVDCR_PLS_LEV7 (0x7U)
#define | ANCTL_PVDENR_PVDE (0x1U << 0)
#define | ANCTL_SARENR_SAREN (0x1U << 0)
#define | ANCTL_USBPCR_USBPEN (0x1U << 0)
#define | ANCTL_USBPCR_DPPUEN (0x1U << 1)
#define | ANCTL_USBPCR_HIGHRESEN (0x1U << 2)
#define | ANCTL_USBPCR_DMSTEN (0x1U << 3)
#define | ANCTL_USBPCR_DPSTEN (0x1U << 4)
#define | ANCTL_CMPACR_PSEL_Msk (0xFU << 0)
#define | ANCTL_CMPACR_NSEL_Msk (0xFU << 4)
#define | ANCTL_CMPACR_CMPAEN (0x1U << 8)
#define | ANCTL_CMPBCR_PSEL_Msk (0xFU << 0)
#define | ANCTL_CMPBCR_NSEL_Msk (0xFU << 4)
#define | ANCTL_CMPBCR_CMPBEN (0x1U << 8)
#define | ANCTL_ISR_MHSIIS (0x1U << 0)
#define | ANCTL_ISR_FHSIIS (0x1U << 1)
#define | ANCTL_ISR_LSIIS (0x1U << 2)
#define | ANCTL_ISR_HSEIS (0x1U << 3)
#define | ANCTL_ISR_LSEIS (0x1U << 4)
#define | ANCTL_ISR_PLLIS (0x1U << 5)
#define | ANCTL_ISR_DCSSIS (0x1U << 7)
#define | ANCTL_IER_MHSIIE (0x1U << 0)
#define | ANCTL_IER_FHSIIE (0x1U << 1)
#define | ANCTL_IER_LSIIE (0x1U << 2)
#define | ANCTL_IER_HSEIE (0x1U << 3)
#define | ANCTL_IER_LSEIE (0x1U << 4)
#define | ANCTL_IER_PLLIE (0x1U << 5)
#define | ANCTL_ICR_MHSIIC (0x1U << 0)
#define | ANCTL_ICR_FHSIIC (0x1U << 1)
#define | ANCTL_ICR_LSIIC (0x1U << 2)
#define | ANCTL_ICR_HSEIC (0x1U << 3)
#define | ANCTL_ICR_LSEIC (0x1U << 4)
#define | ANCTL_ICR_PLLIC (0x1U << 5)
#define | ANCTL_ICR_DCSSIC (0x1U << 7)
#define | ANCTL_DCSSENR_DCSSON (0x1U << 0)
#define | ANCTL_DCSSCR_FREQCNT_Msk (0xFFFU)
#define | RCC_PLLPRE_DIVEN (0x1U << 0)
#define | RCC_PLLPRE_RATIO_Msk (0xFU << 1)
#define | RCC_PLLPRE_RATIO_2 (0x0U << 1)
#define | RCC_PLLPRE_RATIO_3 (0x1U << 1)
#define | RCC_PLLPRE_RATIO_4 (0x2U << 1)
#define | RCC_PLLPRE_RATIO_5 (0x3U << 1)
#define | RCC_PLLPRE_RATIO_6 (0x4U << 1)
#define | RCC_PLLPRE_RATIO_7 (0x5U << 1)
#define | RCC_PLLPRE_RATIO_8 (0x6U << 1)
#define | RCC_PLLPRE_RATIO_9 (0x7U << 1)
#define | RCC_PLLPRE_RATIO_10 (0x8U << 1)
#define | RCC_PLLPRE_RATIO_11 (0x9U << 1)
#define | RCC_PLLPRE_RATIO_12 (0xAU << 1)
#define | RCC_PLLPRE_RATIO_13 (0xBU << 1)
#define | RCC_PLLPRE_RATIO_14 (0xCU << 1)
#define | RCC_PLLPRE_RATIO_15 (0xDU << 1)
#define | RCC_PLLPRE_RATIO_16 (0xEU << 1)
#define | RCC_PLLPRE_SRCEN (0x1U << 5)
#define | RCC_PLLSRC_MHSI (0x0U)
#define | RCC_PLLSRC_HSE (0x1U)
#define | RCC_MAINCLKSRC_MHSI (0x0U)
#define | RCC_MAINCLKSRC_FHSI (0x1U)
#define | RCC_MAINCLKSRC_PLLCLK (0x2U)
#define | RCC_MAINCLKSRC_HSE (0x3U)
#define | RCC_MAINCLKUEN_ENA (0x1U)
#define | RCC_USBPRE_DIVEN (0x1U << 0)
#define | RCC_USBPRE_RATIO_Msk (0x3U << 1)
#define | RCC_USBPRE_RATIO_1_5 (0x2U << 1)
#define | RCC_USBPRE_RATIO_2 (0x0U << 1)
#define | RCC_USBPRE_RATIO_3 (0x1U << 1)
#define | RCC_USBPRE_SRCEN (0x1U << 3)
#define | RCC_AHBPRE_DIVEN (0x1U << 0)
#define | RCC_AHBPRE_RATIO_Msk (0x3FU << 1)
#define | RCC_AHBPRE_RATIO_2 (0x0U << 1)
#define | RCC_AHBPRE_RATIO_3 (0x1U << 1)
#define | RCC_AHBPRE_RATIO_4 (0x2U << 1)
#define | RCC_AHBPRE_RATIO_5 (0x3U << 1)
#define | RCC_AHBPRE_RATIO_6 (0x4U << 1)
#define | RCC_AHBPRE_RATIO_7 (0x5U << 1)
#define | RCC_AHBPRE_RATIO_8 (0x6U << 1)
#define | RCC_AHBPRE_RATIO_9 (0x7U << 1)
#define | RCC_AHBPRE_RATIO_10 (0x8U << 1)
#define | RCC_AHBPRE_RATIO_11 (0x9U << 1)
#define | RCC_AHBPRE_RATIO_12 (0xAU << 1)
#define | RCC_AHBPRE_RATIO_13 (0xBU << 1)
#define | RCC_AHBPRE_RATIO_14 (0xCU << 1)
#define | RCC_AHBPRE_RATIO_15 (0xDU << 1)
#define | RCC_AHBPRE_RATIO_16 (0xEU << 1)
#define | RCC_AHBPRE_RATIO_17 (0xFU << 1)
#define | RCC_AHBPRE_RATIO_18 (0x10U << 1)
#define | RCC_AHBPRE_RATIO_19 (0x11U << 1)
#define | RCC_AHBPRE_RATIO_20 (0x12U << 1)
#define | RCC_AHBPRE_RATIO_21 (0x13U << 1)
#define | RCC_AHBPRE_RATIO_22 (0x14U << 1)
#define | RCC_AHBPRE_RATIO_23 (0x15U << 1)
#define | RCC_AHBPRE_RATIO_24 (0x16U << 1)
#define | RCC_AHBPRE_RATIO_25 (0x17U << 1)
#define | RCC_AHBPRE_RATIO_26 (0x18U << 1)
#define | RCC_AHBPRE_RATIO_27 (0x19U << 1)
#define | RCC_AHBPRE_RATIO_28 (0x1AU << 1)
#define | RCC_AHBPRE_RATIO_29 (0x1BU << 1)
#define | RCC_AHBPRE_RATIO_30 (0x1CU << 1)
#define | RCC_AHBPRE_RATIO_31 (0x1DU << 1)
#define | RCC_AHBPRE_RATIO_32 (0x1EU << 1)
#define | RCC_AHBPRE_RATIO_33 (0x1FU << 1)
#define | RCC_AHBPRE_RATIO_34 (0x20U << 1)
#define | RCC_AHBPRE_RATIO_35 (0x21U << 1)
#define | RCC_AHBPRE_RATIO_36 (0x22U << 1)
#define | RCC_AHBPRE_RATIO_37 (0x23U << 1)
#define | RCC_AHBPRE_RATIO_38 (0x24U << 1)
#define | RCC_AHBPRE_RATIO_39 (0x25U << 1)
#define | RCC_AHBPRE_RATIO_40 (0x26U << 1)
#define | RCC_AHBPRE_RATIO_41 (0x27U << 1)
#define | RCC_AHBPRE_RATIO_42 (0x28U << 1)
#define | RCC_AHBPRE_RATIO_43 (0x29U << 1)
#define | RCC_AHBPRE_RATIO_44 (0x2AU << 1)
#define | RCC_AHBPRE_RATIO_45 (0x2BU << 1)
#define | RCC_AHBPRE_RATIO_46 (0x2CU << 1)
#define | RCC_AHBPRE_RATIO_47 (0x2DU << 1)
#define | RCC_AHBPRE_RATIO_48 (0x2EU << 1)
#define | RCC_AHBPRE_RATIO_49 (0x2FU << 1)
#define | RCC_AHBPRE_RATIO_50 (0x30U << 1)
#define | RCC_AHBPRE_RATIO_51 (0x31U << 1)
#define | RCC_AHBPRE_RATIO_52 (0x32U << 1)
#define | RCC_AHBPRE_RATIO_53 (0x33U << 1)
#define | RCC_AHBPRE_RATIO_54 (0x34U << 1)
#define | RCC_AHBPRE_RATIO_55 (0x35U << 1)
#define | RCC_AHBPRE_RATIO_56 (0x36U << 1)
#define | RCC_AHBPRE_RATIO_57 (0x37U << 1)
#define | RCC_AHBPRE_RATIO_58 (0x38U << 1)
#define | RCC_AHBPRE_RATIO_59 (0x39U << 1)
#define | RCC_AHBPRE_RATIO_60 (0x3AU << 1)
#define | RCC_AHBPRE_RATIO_61 (0x3BU << 1)
#define | RCC_AHBPRE_RATIO_62 (0x3CU << 1)
#define | RCC_AHBPRE_RATIO_63 (0x3DU << 1)
#define | RCC_AHBPRE_RATIO_64 (0x3EU << 1)
#define | RCC_APB1PRE_DIVEN (0x1U << 0)
#define | RCC_APB1PRE_RATIO_Msk (0x3FU << 1)
#define | RCC_APB1PRE_RATIO_2 (0x0U << 1)
#define | RCC_APB1PRE_RATIO_3 (0x1U << 1)
#define | RCC_APB1PRE_RATIO_4 (0x2U << 1)
#define | RCC_APB1PRE_RATIO_5 (0x3U << 1)
#define | RCC_APB1PRE_RATIO_6 (0x4U << 1)
#define | RCC_APB1PRE_RATIO_7 (0x5U << 1)
#define | RCC_APB1PRE_RATIO_8 (0x6U << 1)
#define | RCC_APB1PRE_RATIO_9 (0x7U << 1)
#define | RCC_APB1PRE_RATIO_10 (0x8U << 1)
#define | RCC_APB1PRE_RATIO_11 (0x9U << 1)
#define | RCC_APB1PRE_RATIO_12 (0xAU << 1)
#define | RCC_APB1PRE_RATIO_13 (0xBU << 1)
#define | RCC_APB1PRE_RATIO_14 (0xCU << 1)
#define | RCC_APB1PRE_RATIO_15 (0xDU << 1)
#define | RCC_APB1PRE_RATIO_16 (0xEU << 1)
#define | RCC_APB1PRE_RATIO_17 (0xFU << 1)
#define | RCC_APB1PRE_RATIO_18 (0x10U << 1)
#define | RCC_APB1PRE_RATIO_19 (0x11U << 1)
#define | RCC_APB1PRE_RATIO_20 (0x12U << 1)
#define | RCC_APB1PRE_RATIO_21 (0x13U << 1)
#define | RCC_APB1PRE_RATIO_22 (0x14U << 1)
#define | RCC_APB1PRE_RATIO_23 (0x15U << 1)
#define | RCC_APB1PRE_RATIO_24 (0x16U << 1)
#define | RCC_APB1PRE_RATIO_25 (0x17U << 1)
#define | RCC_APB1PRE_RATIO_26 (0x18U << 1)
#define | RCC_APB1PRE_RATIO_27 (0x19U << 1)
#define | RCC_APB1PRE_RATIO_28 (0x1AU << 1)
#define | RCC_APB1PRE_RATIO_29 (0x1BU << 1)
#define | RCC_APB1PRE_RATIO_30 (0x1CU << 1)
#define | RCC_APB1PRE_RATIO_31 (0x1DU << 1)
#define | RCC_APB1PRE_RATIO_32 (0x1EU << 1)
#define | RCC_APB1PRE_RATIO_33 (0x1FU << 1)
#define | RCC_APB1PRE_RATIO_34 (0x20U << 1)
#define | RCC_APB1PRE_RATIO_35 (0x21U << 1)
#define | RCC_APB1PRE_RATIO_36 (0x22U << 1)
#define | RCC_APB1PRE_RATIO_37 (0x23U << 1)
#define | RCC_APB1PRE_RATIO_38 (0x24U << 1)
#define | RCC_APB1PRE_RATIO_39 (0x25U << 1)
#define | RCC_APB1PRE_RATIO_40 (0x26U << 1)
#define | RCC_APB1PRE_RATIO_41 (0x27U << 1)
#define | RCC_APB1PRE_RATIO_42 (0x28U << 1)
#define | RCC_APB1PRE_RATIO_43 (0x29U << 1)
#define | RCC_APB1PRE_RATIO_44 (0x2AU << 1)
#define | RCC_APB1PRE_RATIO_45 (0x2BU << 1)
#define | RCC_APB1PRE_RATIO_46 (0x2CU << 1)
#define | RCC_APB1PRE_RATIO_47 (0x2DU << 1)
#define | RCC_APB1PRE_RATIO_48 (0x2EU << 1)
#define | RCC_APB1PRE_RATIO_49 (0x2FU << 1)
#define | RCC_APB1PRE_RATIO_50 (0x30U << 1)
#define | RCC_APB1PRE_RATIO_51 (0x31U << 1)
#define | RCC_APB1PRE_RATIO_52 (0x32U << 1)
#define | RCC_APB1PRE_RATIO_53 (0x33U << 1)
#define | RCC_APB1PRE_RATIO_54 (0x34U << 1)
#define | RCC_APB1PRE_RATIO_55 (0x35U << 1)
#define | RCC_APB1PRE_RATIO_56 (0x36U << 1)
#define | RCC_APB1PRE_RATIO_57 (0x37U << 1)
#define | RCC_APB1PRE_RATIO_58 (0x38U << 1)
#define | RCC_APB1PRE_RATIO_59 (0x39U << 1)
#define | RCC_APB1PRE_RATIO_60 (0x3AU << 1)
#define | RCC_APB1PRE_RATIO_61 (0x3BU << 1)
#define | RCC_APB1PRE_RATIO_62 (0x3CU << 1)
#define | RCC_APB1PRE_RATIO_63 (0x3DU << 1)
#define | RCC_APB1PRE_RATIO_64 (0x3EU << 1)
#define | RCC_APB1PRE_SRCEN (0x1U << 7)
#define | RCC_APB2PRE_DIVEN (0x1U << 0)
#define | RCC_APB2PRE_RATIO_Msk (0x3FU << 1)
#define | RCC_APB2PRE_RATIO_2 (0x0U << 1)
#define | RCC_APB2PRE_RATIO_3 (0x1U << 1)
#define | RCC_APB2PRE_RATIO_4 (0x2U << 1)
#define | RCC_APB2PRE_RATIO_5 (0x3U << 1)
#define | RCC_APB2PRE_RATIO_6 (0x4U << 1)
#define | RCC_APB2PRE_RATIO_7 (0x5U << 1)
#define | RCC_APB2PRE_RATIO_8 (0x6U << 1)
#define | RCC_APB2PRE_RATIO_9 (0x7U << 1)
#define | RCC_APB2PRE_RATIO_10 (0x8U << 1)
#define | RCC_APB2PRE_RATIO_11 (0x9U << 1)
#define | RCC_APB2PRE_RATIO_12 (0xAU << 1)
#define | RCC_APB2PRE_RATIO_13 (0xBU << 1)
#define | RCC_APB2PRE_RATIO_14 (0xCU << 1)
#define | RCC_APB2PRE_RATIO_15 (0xDU << 1)
#define | RCC_APB2PRE_RATIO_16 (0xEU << 1)
#define | RCC_APB2PRE_RATIO_17 (0xFU << 1)
#define | RCC_APB2PRE_RATIO_18 (0x10U << 1)
#define | RCC_APB2PRE_RATIO_19 (0x11U << 1)
#define | RCC_APB2PRE_RATIO_20 (0x12U << 1)
#define | RCC_APB2PRE_RATIO_21 (0x13U << 1)
#define | RCC_APB2PRE_RATIO_22 (0x14U << 1)
#define | RCC_APB2PRE_RATIO_23 (0x15U << 1)
#define | RCC_APB2PRE_RATIO_24 (0x16U << 1)
#define | RCC_APB2PRE_RATIO_25 (0x17U << 1)
#define | RCC_APB2PRE_RATIO_26 (0x18U << 1)
#define | RCC_APB2PRE_RATIO_27 (0x19U << 1)
#define | RCC_APB2PRE_RATIO_28 (0x1AU << 1)
#define | RCC_APB2PRE_RATIO_29 (0x1BU << 1)
#define | RCC_APB2PRE_RATIO_30 (0x1CU << 1)
#define | RCC_APB2PRE_RATIO_31 (0x1DU << 1)
#define | RCC_APB2PRE_RATIO_32 (0x1EU << 1)
#define | RCC_APB2PRE_RATIO_33 (0x1FU << 1)
#define | RCC_APB2PRE_RATIO_34 (0x20U << 1)
#define | RCC_APB2PRE_RATIO_35 (0x21U << 1)
#define | RCC_APB2PRE_RATIO_36 (0x22U << 1)
#define | RCC_APB2PRE_RATIO_37 (0x23U << 1)
#define | RCC_APB2PRE_RATIO_38 (0x24U << 1)
#define | RCC_APB2PRE_RATIO_39 (0x25U << 1)
#define | RCC_APB2PRE_RATIO_40 (0x26U << 1)
#define | RCC_APB2PRE_RATIO_41 (0x27U << 1)
#define | RCC_APB2PRE_RATIO_42 (0x28U << 1)
#define | RCC_APB2PRE_RATIO_43 (0x29U << 1)
#define | RCC_APB2PRE_RATIO_44 (0x2AU << 1)
#define | RCC_APB2PRE_RATIO_45 (0x2BU << 1)
#define | RCC_APB2PRE_RATIO_46 (0x2CU << 1)
#define | RCC_APB2PRE_RATIO_47 (0x2DU << 1)
#define | RCC_APB2PRE_RATIO_48 (0x2EU << 1)
#define | RCC_APB2PRE_RATIO_49 (0x2FU << 1)
#define | RCC_APB2PRE_RATIO_50 (0x30U << 1)
#define | RCC_APB2PRE_RATIO_51 (0x31U << 1)
#define | RCC_APB2PRE_RATIO_52 (0x32U << 1)
#define | RCC_APB2PRE_RATIO_53 (0x33U << 1)
#define | RCC_APB2PRE_RATIO_54 (0x34U << 1)
#define | RCC_APB2PRE_RATIO_55 (0x35U << 1)
#define | RCC_APB2PRE_RATIO_56 (0x36U << 1)
#define | RCC_APB2PRE_RATIO_57 (0x37U << 1)
#define | RCC_APB2PRE_RATIO_58 (0x38U << 1)
#define | RCC_APB2PRE_RATIO_59 (0x39U << 1)
#define | RCC_APB2PRE_RATIO_60 (0x3AU << 1)
#define | RCC_APB2PRE_RATIO_61 (0x3BU << 1)
#define | RCC_APB2PRE_RATIO_62 (0x3CU << 1)
#define | RCC_APB2PRE_RATIO_63 (0x3DU << 1)
#define | RCC_APB2PRE_RATIO_64 (0x3EU << 1)
#define | RCC_APB2PRE_SRCEN (0x1U << 7)
#define | RCC_MCLKPRE_DIVEN (0x1U << 0)
#define | RCC_MCLKPRE_RATIO_Msk (0x3FU << 1)
#define | RCC_MCLKPRE_RATIO_2 (0x0U << 1)
#define | RCC_MCLKPRE_RATIO_3 (0x1U << 1)
#define | RCC_MCLKPRE_RATIO_4 (0x2U << 1)
#define | RCC_MCLKPRE_RATIO_5 (0x3U << 1)
#define | RCC_MCLKPRE_RATIO_6 (0x4U << 1)
#define | RCC_MCLKPRE_RATIO_7 (0x5U << 1)
#define | RCC_MCLKPRE_RATIO_8 (0x6U << 1)
#define | RCC_MCLKPRE_RATIO_9 (0x7U << 1)
#define | RCC_MCLKPRE_RATIO_10 (0x8U << 1)
#define | RCC_MCLKPRE_RATIO_11 (0x9U << 1)
#define | RCC_MCLKPRE_RATIO_12 (0xAU << 1)
#define | RCC_MCLKPRE_RATIO_13 (0xBU << 1)
#define | RCC_MCLKPRE_RATIO_14 (0xCU << 1)
#define | RCC_MCLKPRE_RATIO_15 (0xDU << 1)
#define | RCC_MCLKPRE_RATIO_16 (0xEU << 1)
#define | RCC_MCLKPRE_RATIO_17 (0xFU << 1)
#define | RCC_MCLKPRE_RATIO_18 (0x10U << 1)
#define | RCC_MCLKPRE_RATIO_19 (0x11U << 1)
#define | RCC_MCLKPRE_RATIO_20 (0x12U << 1)
#define | RCC_MCLKPRE_RATIO_21 (0x13U << 1)
#define | RCC_MCLKPRE_RATIO_22 (0x14U << 1)
#define | RCC_MCLKPRE_RATIO_23 (0x15U << 1)
#define | RCC_MCLKPRE_RATIO_24 (0x16U << 1)
#define | RCC_MCLKPRE_RATIO_25 (0x17U << 1)
#define | RCC_MCLKPRE_RATIO_26 (0x18U << 1)
#define | RCC_MCLKPRE_RATIO_27 (0x19U << 1)
#define | RCC_MCLKPRE_RATIO_28 (0x1AU << 1)
#define | RCC_MCLKPRE_RATIO_29 (0x1BU << 1)
#define | RCC_MCLKPRE_RATIO_30 (0x1CU << 1)
#define | RCC_MCLKPRE_RATIO_31 (0x1DU << 1)
#define | RCC_MCLKPRE_RATIO_32 (0x1EU << 1)
#define | RCC_MCLKPRE_RATIO_33 (0x1FU << 1)
#define | RCC_MCLKPRE_RATIO_34 (0x20U << 1)
#define | RCC_MCLKPRE_RATIO_35 (0x21U << 1)
#define | RCC_MCLKPRE_RATIO_36 (0x22U << 1)
#define | RCC_MCLKPRE_RATIO_37 (0x23U << 1)
#define | RCC_MCLKPRE_RATIO_38 (0x24U << 1)
#define | RCC_MCLKPRE_RATIO_39 (0x25U << 1)
#define | RCC_MCLKPRE_RATIO_40 (0x26U << 1)
#define | RCC_MCLKPRE_RATIO_41 (0x27U << 1)
#define | RCC_MCLKPRE_RATIO_42 (0x28U << 1)
#define | RCC_MCLKPRE_RATIO_43 (0x29U << 1)
#define | RCC_MCLKPRE_RATIO_44 (0x2AU << 1)
#define | RCC_MCLKPRE_RATIO_45 (0x2BU << 1)
#define | RCC_MCLKPRE_RATIO_46 (0x2CU << 1)
#define | RCC_MCLKPRE_RATIO_47 (0x2DU << 1)
#define | RCC_MCLKPRE_RATIO_48 (0x2EU << 1)
#define | RCC_MCLKPRE_RATIO_49 (0x2FU << 1)
#define | RCC_MCLKPRE_RATIO_50 (0x30U << 1)
#define | RCC_MCLKPRE_RATIO_51 (0x31U << 1)
#define | RCC_MCLKPRE_RATIO_52 (0x32U << 1)
#define | RCC_MCLKPRE_RATIO_53 (0x33U << 1)
#define | RCC_MCLKPRE_RATIO_54 (0x34U << 1)
#define | RCC_MCLKPRE_RATIO_55 (0x35U << 1)
#define | RCC_MCLKPRE_RATIO_56 (0x36U << 1)
#define | RCC_MCLKPRE_RATIO_57 (0x37U << 1)
#define | RCC_MCLKPRE_RATIO_58 (0x38U << 1)
#define | RCC_MCLKPRE_RATIO_59 (0x39U << 1)
#define | RCC_MCLKPRE_RATIO_60 (0x3AU << 1)
#define | RCC_MCLKPRE_RATIO_61 (0x3BU << 1)
#define | RCC_MCLKPRE_RATIO_62 (0x3CU << 1)
#define | RCC_MCLKPRE_RATIO_63 (0x3DU << 1)
#define | RCC_MCLKPRE_RATIO_64 (0x3EU << 1)
#define | RCC_MCLKPRE_SRCEN (0x1U << 7)
#define | RCC_I2SPRE_DIVEN (0x1U << 0)
#define | RCC_I2SPRE_RATIO_Msk (0x1FFU << 1)
#define | RCC_I2SPRE_RATIO_2 (0x0U << 1)
#define | RCC_I2SPRE_RATIO_3 (0x1U << 1)
#define | RCC_I2SPRE_RATIO_4 (0x2U << 1)
#define | RCC_I2SPRE_RATIO_5 (0x3U << 1)
#define | RCC_I2SPRE_RATIO_6 (0x4U << 1)
#define | RCC_I2SPRE_RATIO_7 (0x5U << 1)
#define | RCC_I2SPRE_RATIO_8 (0x6U << 1)
#define | RCC_I2SPRE_RATIO_9 (0x7U << 1)
#define | RCC_I2SPRE_RATIO_10 (0x8U << 1)
#define | RCC_I2SPRE_RATIO_11 (0x9U << 1)
#define | RCC_I2SPRE_RATIO_12 (0xAU << 1)
#define | RCC_I2SPRE_RATIO_13 (0xBU << 1)
#define | RCC_I2SPRE_RATIO_14 (0xCU << 1)
#define | RCC_I2SPRE_RATIO_15 (0xDU << 1)
#define | RCC_I2SPRE_RATIO_16 (0xEU << 1)
#define | RCC_I2SPRE_RATIO_17 (0xFU << 1)
#define | RCC_I2SPRE_RATIO_18 (0x10U << 1)
#define | RCC_I2SPRE_RATIO_19 (0x11U << 1)
#define | RCC_I2SPRE_RATIO_20 (0x12U << 1)
#define | RCC_I2SPRE_RATIO_21 (0x13U << 1)
#define | RCC_I2SPRE_RATIO_22 (0x14U << 1)
#define | RCC_I2SPRE_RATIO_23 (0x15U << 1)
#define | RCC_I2SPRE_RATIO_24 (0x16U << 1)
#define | RCC_I2SPRE_RATIO_25 (0x17U << 1)
#define | RCC_I2SPRE_RATIO_26 (0x18U << 1)
#define | RCC_I2SPRE_RATIO_27 (0x19U << 1)
#define | RCC_I2SPRE_RATIO_28 (0x1AU << 1)
#define | RCC_I2SPRE_RATIO_29 (0x1BU << 1)
#define | RCC_I2SPRE_RATIO_30 (0x1CU << 1)
#define | RCC_I2SPRE_RATIO_31 (0x1DU << 1)
#define | RCC_I2SPRE_RATIO_32 (0x1EU << 1)
#define | RCC_I2SPRE_RATIO_33 (0x1FU << 1)
#define | RCC_I2SPRE_RATIO_34 (0x20U << 1)
#define | RCC_I2SPRE_RATIO_35 (0x21U << 1)
#define | RCC_I2SPRE_RATIO_36 (0x22U << 1)
#define | RCC_I2SPRE_RATIO_37 (0x23U << 1)
#define | RCC_I2SPRE_RATIO_38 (0x24U << 1)
#define | RCC_I2SPRE_RATIO_39 (0x25U << 1)
#define | RCC_I2SPRE_RATIO_40 (0x26U << 1)
#define | RCC_I2SPRE_RATIO_41 (0x27U << 1)
#define | RCC_I2SPRE_RATIO_42 (0x28U << 1)
#define | RCC_I2SPRE_RATIO_43 (0x29U << 1)
#define | RCC_I2SPRE_RATIO_44 (0x2AU << 1)
#define | RCC_I2SPRE_RATIO_45 (0x2BU << 1)
#define | RCC_I2SPRE_RATIO_46 (0x2CU << 1)
#define | RCC_I2SPRE_RATIO_47 (0x2DU << 1)
#define | RCC_I2SPRE_RATIO_48 (0x2EU << 1)
#define | RCC_I2SPRE_RATIO_49 (0x2FU << 1)
#define | RCC_I2SPRE_RATIO_50 (0x30U << 1)
#define | RCC_I2SPRE_RATIO_51 (0x31U << 1)
#define | RCC_I2SPRE_RATIO_52 (0x32U << 1)
#define | RCC_I2SPRE_RATIO_53 (0x33U << 1)
#define | RCC_I2SPRE_RATIO_54 (0x34U << 1)
#define | RCC_I2SPRE_RATIO_55 (0x35U << 1)
#define | RCC_I2SPRE_RATIO_56 (0x36U << 1)
#define | RCC_I2SPRE_RATIO_57 (0x37U << 1)
#define | RCC_I2SPRE_RATIO_58 (0x38U << 1)
#define | RCC_I2SPRE_RATIO_59 (0x39U << 1)
#define | RCC_I2SPRE_RATIO_60 (0x3AU << 1)
#define | RCC_I2SPRE_RATIO_61 (0x3BU << 1)
#define | RCC_I2SPRE_RATIO_62 (0x3CU << 1)
#define | RCC_I2SPRE_RATIO_63 (0x3DU << 1)
#define | RCC_I2SPRE_RATIO_64 (0x3EU << 1)
#define | RCC_I2SPRE_RATIO_65 (0x3FU << 1)
#define | RCC_I2SPRE_RATIO_66 (0x40U << 1)
#define | RCC_I2SPRE_RATIO_67 (0x41U << 1)
#define | RCC_I2SPRE_RATIO_68 (0x42U << 1)
#define | RCC_I2SPRE_RATIO_69 (0x43U << 1)
#define | RCC_I2SPRE_RATIO_70 (0x44U << 1)
#define | RCC_I2SPRE_RATIO_71 (0x45U << 1)
#define | RCC_I2SPRE_RATIO_72 (0x46U << 1)
#define | RCC_I2SPRE_RATIO_73 (0x47U << 1)
#define | RCC_I2SPRE_RATIO_74 (0x48U << 1)
#define | RCC_I2SPRE_RATIO_75 (0x49U << 1)
#define | RCC_I2SPRE_RATIO_76 (0x4AU << 1)
#define | RCC_I2SPRE_RATIO_77 (0x4BU << 1)
#define | RCC_I2SPRE_RATIO_78 (0x4CU << 1)
#define | RCC_I2SPRE_RATIO_79 (0x4DU << 1)
#define | RCC_I2SPRE_RATIO_80 (0x4EU << 1)
#define | RCC_I2SPRE_RATIO_81 (0x4FU << 1)
#define | RCC_I2SPRE_RATIO_82 (0x50U << 1)
#define | RCC_I2SPRE_RATIO_83 (0x51U << 1)
#define | RCC_I2SPRE_RATIO_84 (0x52U << 1)
#define | RCC_I2SPRE_RATIO_85 (0x53U << 1)
#define | RCC_I2SPRE_RATIO_86 (0x54U << 1)
#define | RCC_I2SPRE_RATIO_87 (0x55U << 1)
#define | RCC_I2SPRE_RATIO_88 (0x56U << 1)
#define | RCC_I2SPRE_RATIO_89 (0x57U << 1)
#define | RCC_I2SPRE_RATIO_90 (0x58U << 1)
#define | RCC_I2SPRE_RATIO_91 (0x59U << 1)
#define | RCC_I2SPRE_RATIO_92 (0x5AU << 1)
#define | RCC_I2SPRE_RATIO_93 (0x5BU << 1)
#define | RCC_I2SPRE_RATIO_94 (0x5CU << 1)
#define | RCC_I2SPRE_RATIO_95 (0x5DU << 1)
#define | RCC_I2SPRE_RATIO_96 (0x5EU << 1)
#define | RCC_I2SPRE_RATIO_97 (0x5FU << 1)
#define | RCC_I2SPRE_RATIO_98 (0x60U << 1)
#define | RCC_I2SPRE_RATIO_99 (0x61U << 1)
#define | RCC_I2SPRE_RATIO_100 (0x62U << 1)
#define | RCC_I2SPRE_RATIO_101 (0x63U << 1)
#define | RCC_I2SPRE_RATIO_102 (0x64U << 1)
#define | RCC_I2SPRE_RATIO_103 (0x65U << 1)
#define | RCC_I2SPRE_RATIO_104 (0x66U << 1)
#define | RCC_I2SPRE_RATIO_105 (0x67U << 1)
#define | RCC_I2SPRE_RATIO_106 (0x68U << 1)
#define | RCC_I2SPRE_RATIO_107 (0x69U << 1)
#define | RCC_I2SPRE_RATIO_108 (0x6AU << 1)
#define | RCC_I2SPRE_RATIO_109 (0x6BU << 1)
#define | RCC_I2SPRE_RATIO_110 (0x6CU << 1)
#define | RCC_I2SPRE_RATIO_111 (0x6DU << 1)
#define | RCC_I2SPRE_RATIO_112 (0x6EU << 1)
#define | RCC_I2SPRE_RATIO_113 (0x6FU << 1)
#define | RCC_I2SPRE_RATIO_114 (0x70U << 1)
#define | RCC_I2SPRE_RATIO_115 (0x71U << 1)
#define | RCC_I2SPRE_RATIO_116 (0x72U << 1)
#define | RCC_I2SPRE_RATIO_117 (0x73U << 1)
#define | RCC_I2SPRE_RATIO_118 (0x74U << 1)
#define | RCC_I2SPRE_RATIO_119 (0x75U << 1)
#define | RCC_I2SPRE_RATIO_120 (0x76U << 1)
#define | RCC_I2SPRE_RATIO_121 (0x77U << 1)
#define | RCC_I2SPRE_RATIO_122 (0x78U << 1)
#define | RCC_I2SPRE_RATIO_123 (0x79U << 1)
#define | RCC_I2SPRE_RATIO_124 (0x7AU << 1)
#define | RCC_I2SPRE_RATIO_125 (0x7BU << 1)
#define | RCC_I2SPRE_RATIO_126 (0x7CU << 1)
#define | RCC_I2SPRE_RATIO_127 (0x7DU << 1)
#define | RCC_I2SPRE_RATIO_128 (0x7EU << 1)
#define | RCC_I2SPRE_RATIO_129 (0x7FU << 1)
#define | RCC_I2SPRE_RATIO_130 (0x80U << 1)
#define | RCC_I2SPRE_RATIO_131 (0x81U << 1)
#define | RCC_I2SPRE_RATIO_132 (0x82U << 1)
#define | RCC_I2SPRE_RATIO_133 (0x83U << 1)
#define | RCC_I2SPRE_RATIO_134 (0x84U << 1)
#define | RCC_I2SPRE_RATIO_135 (0x85U << 1)
#define | RCC_I2SPRE_RATIO_136 (0x86U << 1)
#define | RCC_I2SPRE_RATIO_137 (0x87U << 1)
#define | RCC_I2SPRE_RATIO_138 (0x88U << 1)
#define | RCC_I2SPRE_RATIO_139 (0x89U << 1)
#define | RCC_I2SPRE_RATIO_140 (0x8AU << 1)
#define | RCC_I2SPRE_RATIO_141 (0x8BU << 1)
#define | RCC_I2SPRE_RATIO_142 (0x8CU << 1)
#define | RCC_I2SPRE_RATIO_143 (0x8DU << 1)
#define | RCC_I2SPRE_RATIO_144 (0x8EU << 1)
#define | RCC_I2SPRE_RATIO_145 (0x8FU << 1)
#define | RCC_I2SPRE_RATIO_146 (0x90U << 1)
#define | RCC_I2SPRE_RATIO_147 (0x91U << 1)
#define | RCC_I2SPRE_RATIO_148 (0x92U << 1)
#define | RCC_I2SPRE_RATIO_149 (0x93U << 1)
#define | RCC_I2SPRE_RATIO_150 (0x94U << 1)
#define | RCC_I2SPRE_RATIO_151 (0x95U << 1)
#define | RCC_I2SPRE_RATIO_152 (0x96U << 1)
#define | RCC_I2SPRE_RATIO_153 (0x97U << 1)
#define | RCC_I2SPRE_RATIO_154 (0x98U << 1)
#define | RCC_I2SPRE_RATIO_155 (0x99U << 1)
#define | RCC_I2SPRE_RATIO_156 (0x9AU << 1)
#define | RCC_I2SPRE_RATIO_157 (0x9BU << 1)
#define | RCC_I2SPRE_RATIO_158 (0x9CU << 1)
#define | RCC_I2SPRE_RATIO_159 (0x9DU << 1)
#define | RCC_I2SPRE_RATIO_160 (0x9EU << 1)
#define | RCC_I2SPRE_RATIO_161 (0x9FU << 1)
#define | RCC_I2SPRE_RATIO_162 (0xA0U << 1)
#define | RCC_I2SPRE_RATIO_163 (0xA1U << 1)
#define | RCC_I2SPRE_RATIO_164 (0xA2U << 1)
#define | RCC_I2SPRE_RATIO_165 (0xA3U << 1)
#define | RCC_I2SPRE_RATIO_166 (0xA4U << 1)
#define | RCC_I2SPRE_RATIO_167 (0xA5U << 1)
#define | RCC_I2SPRE_RATIO_168 (0xA6U << 1)
#define | RCC_I2SPRE_RATIO_169 (0xA7U << 1)
#define | RCC_I2SPRE_RATIO_170 (0xA8U << 1)
#define | RCC_I2SPRE_RATIO_171 (0xA9U << 1)
#define | RCC_I2SPRE_RATIO_172 (0xAAU << 1)
#define | RCC_I2SPRE_RATIO_173 (0xABU << 1)
#define | RCC_I2SPRE_RATIO_174 (0xACU << 1)
#define | RCC_I2SPRE_RATIO_175 (0xADU << 1)
#define | RCC_I2SPRE_RATIO_176 (0xAEU << 1)
#define | RCC_I2SPRE_RATIO_177 (0xAFU << 1)
#define | RCC_I2SPRE_RATIO_178 (0xB0U << 1)
#define | RCC_I2SPRE_RATIO_179 (0xB1U << 1)
#define | RCC_I2SPRE_RATIO_180 (0xB2U << 1)
#define | RCC_I2SPRE_RATIO_181 (0xB3U << 1)
#define | RCC_I2SPRE_RATIO_182 (0xB4U << 1)
#define | RCC_I2SPRE_RATIO_183 (0xB5U << 1)
#define | RCC_I2SPRE_RATIO_184 (0xB6U << 1)
#define | RCC_I2SPRE_RATIO_185 (0xB7U << 1)
#define | RCC_I2SPRE_RATIO_186 (0xB8U << 1)
#define | RCC_I2SPRE_RATIO_187 (0xB9U << 1)
#define | RCC_I2SPRE_RATIO_188 (0xBAU << 1)
#define | RCC_I2SPRE_RATIO_189 (0xBBU << 1)
#define | RCC_I2SPRE_RATIO_190 (0xBCU << 1)
#define | RCC_I2SPRE_RATIO_191 (0xBDU << 1)
#define | RCC_I2SPRE_RATIO_192 (0xBEU << 1)
#define | RCC_I2SPRE_RATIO_193 (0xBFU << 1)
#define | RCC_I2SPRE_RATIO_194 (0xC0U << 1)
#define | RCC_I2SPRE_RATIO_195 (0xC1U << 1)
#define | RCC_I2SPRE_RATIO_196 (0xC2U << 1)
#define | RCC_I2SPRE_RATIO_197 (0xC3U << 1)
#define | RCC_I2SPRE_RATIO_198 (0xC4U << 1)
#define | RCC_I2SPRE_RATIO_199 (0xC5U << 1)
#define | RCC_I2SPRE_RATIO_200 (0xC6U << 1)
#define | RCC_I2SPRE_RATIO_201 (0xC7U << 1)
#define | RCC_I2SPRE_RATIO_202 (0xC8U << 1)
#define | RCC_I2SPRE_RATIO_203 (0xC9U << 1)
#define | RCC_I2SPRE_RATIO_204 (0xCAU << 1)
#define | RCC_I2SPRE_RATIO_205 (0xCBU << 1)
#define | RCC_I2SPRE_RATIO_206 (0xCCU << 1)
#define | RCC_I2SPRE_RATIO_207 (0xCDU << 1)
#define | RCC_I2SPRE_RATIO_208 (0xCEU << 1)
#define | RCC_I2SPRE_RATIO_209 (0xCFU << 1)
#define | RCC_I2SPRE_RATIO_210 (0xD0U << 1)
#define | RCC_I2SPRE_RATIO_211 (0xD1U << 1)
#define | RCC_I2SPRE_RATIO_212 (0xD2U << 1)
#define | RCC_I2SPRE_RATIO_213 (0xD3U << 1)
#define | RCC_I2SPRE_RATIO_214 (0xD4U << 1)
#define | RCC_I2SPRE_RATIO_215 (0xD5U << 1)
#define | RCC_I2SPRE_RATIO_216 (0xD6U << 1)
#define | RCC_I2SPRE_RATIO_217 (0xD7U << 1)
#define | RCC_I2SPRE_RATIO_218 (0xD8U << 1)
#define | RCC_I2SPRE_RATIO_219 (0xD9U << 1)
#define | RCC_I2SPRE_RATIO_220 (0xDAU << 1)
#define | RCC_I2SPRE_RATIO_221 (0xDBU << 1)
#define | RCC_I2SPRE_RATIO_222 (0xDCU << 1)
#define | RCC_I2SPRE_RATIO_223 (0xDDU << 1)
#define | RCC_I2SPRE_RATIO_224 (0xDEU << 1)
#define | RCC_I2SPRE_RATIO_225 (0xDFU << 1)
#define | RCC_I2SPRE_RATIO_226 (0xE0U << 1)
#define | RCC_I2SPRE_RATIO_227 (0xE1U << 1)
#define | RCC_I2SPRE_RATIO_228 (0xE2U << 1)
#define | RCC_I2SPRE_RATIO_229 (0xE3U << 1)
#define | RCC_I2SPRE_RATIO_230 (0xE4U << 1)
#define | RCC_I2SPRE_RATIO_231 (0xE5U << 1)
#define | RCC_I2SPRE_RATIO_232 (0xE6U << 1)
#define | RCC_I2SPRE_RATIO_233 (0xE7U << 1)
#define | RCC_I2SPRE_RATIO_234 (0xE8U << 1)
#define | RCC_I2SPRE_RATIO_235 (0xE9U << 1)
#define | RCC_I2SPRE_RATIO_236 (0xEAU << 1)
#define | RCC_I2SPRE_RATIO_237 (0xEBU << 1)
#define | RCC_I2SPRE_RATIO_238 (0xECU << 1)
#define | RCC_I2SPRE_RATIO_239 (0xEDU << 1)
#define | RCC_I2SPRE_RATIO_240 (0xEEU << 1)
#define | RCC_I2SPRE_RATIO_241 (0xEFU << 1)
#define | RCC_I2SPRE_RATIO_242 (0xF0U << 1)
#define | RCC_I2SPRE_RATIO_243 (0xF1U << 1)
#define | RCC_I2SPRE_RATIO_244 (0xF2U << 1)
#define | RCC_I2SPRE_RATIO_245 (0xF3U << 1)
#define | RCC_I2SPRE_RATIO_246 (0xF4U << 1)
#define | RCC_I2SPRE_RATIO_247 (0xF5U << 1)
#define | RCC_I2SPRE_RATIO_248 (0xF6U << 1)
#define | RCC_I2SPRE_RATIO_249 (0xF7U << 1)
#define | RCC_I2SPRE_RATIO_250 (0xF8U << 1)
#define | RCC_I2SPRE_RATIO_251 (0xF9U << 1)
#define | RCC_I2SPRE_RATIO_252 (0xFAU << 1)
#define | RCC_I2SPRE_RATIO_253 (0xFBU << 1)
#define | RCC_I2SPRE_RATIO_254 (0xFCU << 1)
#define | RCC_I2SPRE_RATIO_255 (0xFDU << 1)
#define | RCC_I2SPRE_RATIO_256 (0xFEU << 1)
#define | RCC_I2SPRE_RATIO_257 (0xFFU << 1)
#define | RCC_I2SPRE_RATIO_258 (0x100U << 1)
#define | RCC_I2SPRE_RATIO_259 (0x101U << 1)
#define | RCC_I2SPRE_RATIO_260 (0x102U << 1)
#define | RCC_I2SPRE_RATIO_261 (0x103U << 1)
#define | RCC_I2SPRE_RATIO_262 (0x104U << 1)
#define | RCC_I2SPRE_RATIO_263 (0x105U << 1)
#define | RCC_I2SPRE_RATIO_264 (0x106U << 1)
#define | RCC_I2SPRE_RATIO_265 (0x107U << 1)
#define | RCC_I2SPRE_RATIO_266 (0x108U << 1)
#define | RCC_I2SPRE_RATIO_267 (0x109U << 1)
#define | RCC_I2SPRE_RATIO_268 (0x10AU << 1)
#define | RCC_I2SPRE_RATIO_269 (0x10BU << 1)
#define | RCC_I2SPRE_RATIO_270 (0x10CU << 1)
#define | RCC_I2SPRE_RATIO_271 (0x10DU << 1)
#define | RCC_I2SPRE_RATIO_272 (0x10EU << 1)
#define | RCC_I2SPRE_RATIO_273 (0x10FU << 1)
#define | RCC_I2SPRE_RATIO_274 (0x110U << 1)
#define | RCC_I2SPRE_RATIO_275 (0x111U << 1)
#define | RCC_I2SPRE_RATIO_276 (0x112U << 1)
#define | RCC_I2SPRE_RATIO_277 (0x113U << 1)
#define | RCC_I2SPRE_RATIO_278 (0x114U << 1)
#define | RCC_I2SPRE_RATIO_279 (0x115U << 1)
#define | RCC_I2SPRE_RATIO_280 (0x116U << 1)
#define | RCC_I2SPRE_RATIO_281 (0x117U << 1)
#define | RCC_I2SPRE_RATIO_282 (0x118U << 1)
#define | RCC_I2SPRE_RATIO_283 (0x119U << 1)
#define | RCC_I2SPRE_RATIO_284 (0x11AU << 1)
#define | RCC_I2SPRE_RATIO_285 (0x11BU << 1)
#define | RCC_I2SPRE_RATIO_286 (0x11CU << 1)
#define | RCC_I2SPRE_RATIO_287 (0x11DU << 1)
#define | RCC_I2SPRE_RATIO_288 (0x11EU << 1)
#define | RCC_I2SPRE_RATIO_289 (0x11FU << 1)
#define | RCC_I2SPRE_RATIO_290 (0x120U << 1)
#define | RCC_I2SPRE_RATIO_291 (0x121U << 1)
#define | RCC_I2SPRE_RATIO_292 (0x122U << 1)
#define | RCC_I2SPRE_RATIO_293 (0x123U << 1)
#define | RCC_I2SPRE_RATIO_294 (0x124U << 1)
#define | RCC_I2SPRE_RATIO_295 (0x125U << 1)
#define | RCC_I2SPRE_RATIO_296 (0x126U << 1)
#define | RCC_I2SPRE_RATIO_297 (0x127U << 1)
#define | RCC_I2SPRE_RATIO_298 (0x128U << 1)
#define | RCC_I2SPRE_RATIO_299 (0x129U << 1)
#define | RCC_I2SPRE_RATIO_300 (0x12AU << 1)
#define | RCC_I2SPRE_RATIO_301 (0x12BU << 1)
#define | RCC_I2SPRE_RATIO_302 (0x12CU << 1)
#define | RCC_I2SPRE_RATIO_303 (0x12DU << 1)
#define | RCC_I2SPRE_RATIO_304 (0x12EU << 1)
#define | RCC_I2SPRE_RATIO_305 (0x12FU << 1)
#define | RCC_I2SPRE_RATIO_306 (0x130U << 1)
#define | RCC_I2SPRE_RATIO_307 (0x131U << 1)
#define | RCC_I2SPRE_RATIO_308 (0x132U << 1)
#define | RCC_I2SPRE_RATIO_309 (0x133U << 1)
#define | RCC_I2SPRE_RATIO_310 (0x134U << 1)
#define | RCC_I2SPRE_RATIO_311 (0x135U << 1)
#define | RCC_I2SPRE_RATIO_312 (0x136U << 1)
#define | RCC_I2SPRE_RATIO_313 (0x137U << 1)
#define | RCC_I2SPRE_RATIO_314 (0x138U << 1)
#define | RCC_I2SPRE_RATIO_315 (0x139U << 1)
#define | RCC_I2SPRE_RATIO_316 (0x13AU << 1)
#define | RCC_I2SPRE_RATIO_317 (0x13BU << 1)
#define | RCC_I2SPRE_RATIO_318 (0x13CU << 1)
#define | RCC_I2SPRE_RATIO_319 (0x13DU << 1)
#define | RCC_I2SPRE_RATIO_320 (0x13EU << 1)
#define | RCC_I2SPRE_RATIO_321 (0x13FU << 1)
#define | RCC_I2SPRE_RATIO_322 (0x140U << 1)
#define | RCC_I2SPRE_RATIO_323 (0x141U << 1)
#define | RCC_I2SPRE_RATIO_324 (0x142U << 1)
#define | RCC_I2SPRE_RATIO_325 (0x143U << 1)
#define | RCC_I2SPRE_RATIO_326 (0x144U << 1)
#define | RCC_I2SPRE_RATIO_327 (0x145U << 1)
#define | RCC_I2SPRE_RATIO_328 (0x146U << 1)
#define | RCC_I2SPRE_RATIO_329 (0x147U << 1)
#define | RCC_I2SPRE_RATIO_330 (0x148U << 1)
#define | RCC_I2SPRE_RATIO_331 (0x149U << 1)
#define | RCC_I2SPRE_RATIO_332 (0x14AU << 1)
#define | RCC_I2SPRE_RATIO_333 (0x14BU << 1)
#define | RCC_I2SPRE_RATIO_334 (0x14CU << 1)
#define | RCC_I2SPRE_RATIO_335 (0x14DU << 1)
#define | RCC_I2SPRE_RATIO_336 (0x14EU << 1)
#define | RCC_I2SPRE_RATIO_337 (0x14FU << 1)
#define | RCC_I2SPRE_RATIO_338 (0x150U << 1)
#define | RCC_I2SPRE_RATIO_339 (0x151U << 1)
#define | RCC_I2SPRE_RATIO_340 (0x152U << 1)
#define | RCC_I2SPRE_RATIO_341 (0x153U << 1)
#define | RCC_I2SPRE_RATIO_342 (0x154U << 1)
#define | RCC_I2SPRE_RATIO_343 (0x155U << 1)
#define | RCC_I2SPRE_RATIO_344 (0x156U << 1)
#define | RCC_I2SPRE_RATIO_345 (0x157U << 1)
#define | RCC_I2SPRE_RATIO_346 (0x158U << 1)
#define | RCC_I2SPRE_RATIO_347 (0x159U << 1)
#define | RCC_I2SPRE_RATIO_348 (0x15AU << 1)
#define | RCC_I2SPRE_RATIO_349 (0x15BU << 1)
#define | RCC_I2SPRE_RATIO_350 (0x15CU << 1)
#define | RCC_I2SPRE_RATIO_351 (0x15DU << 1)
#define | RCC_I2SPRE_RATIO_352 (0x15EU << 1)
#define | RCC_I2SPRE_RATIO_353 (0x15FU << 1)
#define | RCC_I2SPRE_RATIO_354 (0x160U << 1)
#define | RCC_I2SPRE_RATIO_355 (0x161U << 1)
#define | RCC_I2SPRE_RATIO_356 (0x162U << 1)
#define | RCC_I2SPRE_RATIO_357 (0x163U << 1)
#define | RCC_I2SPRE_RATIO_358 (0x164U << 1)
#define | RCC_I2SPRE_RATIO_359 (0x165U << 1)
#define | RCC_I2SPRE_RATIO_360 (0x166U << 1)
#define | RCC_I2SPRE_RATIO_361 (0x167U << 1)
#define | RCC_I2SPRE_RATIO_362 (0x168U << 1)
#define | RCC_I2SPRE_RATIO_363 (0x169U << 1)
#define | RCC_I2SPRE_RATIO_364 (0x16AU << 1)
#define | RCC_I2SPRE_RATIO_365 (0x16BU << 1)
#define | RCC_I2SPRE_RATIO_366 (0x16CU << 1)
#define | RCC_I2SPRE_RATIO_367 (0x16DU << 1)
#define | RCC_I2SPRE_RATIO_368 (0x16EU << 1)
#define | RCC_I2SPRE_RATIO_369 (0x16FU << 1)
#define | RCC_I2SPRE_RATIO_370 (0x170U << 1)
#define | RCC_I2SPRE_RATIO_371 (0x171U << 1)
#define | RCC_I2SPRE_RATIO_372 (0x172U << 1)
#define | RCC_I2SPRE_RATIO_373 (0x173U << 1)
#define | RCC_I2SPRE_RATIO_374 (0x174U << 1)
#define | RCC_I2SPRE_RATIO_375 (0x175U << 1)
#define | RCC_I2SPRE_RATIO_376 (0x176U << 1)
#define | RCC_I2SPRE_RATIO_377 (0x177U << 1)
#define | RCC_I2SPRE_RATIO_378 (0x178U << 1)
#define | RCC_I2SPRE_RATIO_379 (0x179U << 1)
#define | RCC_I2SPRE_RATIO_380 (0x17AU << 1)
#define | RCC_I2SPRE_RATIO_381 (0x17BU << 1)
#define | RCC_I2SPRE_RATIO_382 (0x17CU << 1)
#define | RCC_I2SPRE_RATIO_383 (0x17DU << 1)
#define | RCC_I2SPRE_RATIO_384 (0x17EU << 1)
#define | RCC_I2SPRE_RATIO_385 (0x17FU << 1)
#define | RCC_I2SPRE_RATIO_386 (0x180U << 1)
#define | RCC_I2SPRE_RATIO_387 (0x181U << 1)
#define | RCC_I2SPRE_RATIO_388 (0x182U << 1)
#define | RCC_I2SPRE_RATIO_389 (0x183U << 1)
#define | RCC_I2SPRE_RATIO_390 (0x184U << 1)
#define | RCC_I2SPRE_RATIO_391 (0x185U << 1)
#define | RCC_I2SPRE_RATIO_392 (0x186U << 1)
#define | RCC_I2SPRE_RATIO_393 (0x187U << 1)
#define | RCC_I2SPRE_RATIO_394 (0x188U << 1)
#define | RCC_I2SPRE_RATIO_395 (0x189U << 1)
#define | RCC_I2SPRE_RATIO_396 (0x18AU << 1)
#define | RCC_I2SPRE_RATIO_397 (0x18BU << 1)
#define | RCC_I2SPRE_RATIO_398 (0x18CU << 1)
#define | RCC_I2SPRE_RATIO_399 (0x18DU << 1)
#define | RCC_I2SPRE_RATIO_400 (0x18EU << 1)
#define | RCC_I2SPRE_RATIO_401 (0x18FU << 1)
#define | RCC_I2SPRE_RATIO_402 (0x190U << 1)
#define | RCC_I2SPRE_RATIO_403 (0x191U << 1)
#define | RCC_I2SPRE_RATIO_404 (0x192U << 1)
#define | RCC_I2SPRE_RATIO_405 (0x193U << 1)
#define | RCC_I2SPRE_RATIO_406 (0x194U << 1)
#define | RCC_I2SPRE_RATIO_407 (0x195U << 1)
#define | RCC_I2SPRE_RATIO_408 (0x196U << 1)
#define | RCC_I2SPRE_RATIO_409 (0x197U << 1)
#define | RCC_I2SPRE_RATIO_410 (0x198U << 1)
#define | RCC_I2SPRE_RATIO_411 (0x199U << 1)
#define | RCC_I2SPRE_RATIO_412 (0x19AU << 1)
#define | RCC_I2SPRE_RATIO_413 (0x19BU << 1)
#define | RCC_I2SPRE_RATIO_414 (0x19CU << 1)
#define | RCC_I2SPRE_RATIO_415 (0x19DU << 1)
#define | RCC_I2SPRE_RATIO_416 (0x19EU << 1)
#define | RCC_I2SPRE_RATIO_417 (0x19FU << 1)
#define | RCC_I2SPRE_RATIO_418 (0x1A0U << 1)
#define | RCC_I2SPRE_RATIO_419 (0x1A1U << 1)
#define | RCC_I2SPRE_RATIO_420 (0x1A2U << 1)
#define | RCC_I2SPRE_RATIO_421 (0x1A3U << 1)
#define | RCC_I2SPRE_RATIO_422 (0x1A4U << 1)
#define | RCC_I2SPRE_RATIO_423 (0x1A5U << 1)
#define | RCC_I2SPRE_RATIO_424 (0x1A6U << 1)
#define | RCC_I2SPRE_RATIO_425 (0x1A7U << 1)
#define | RCC_I2SPRE_RATIO_426 (0x1A8U << 1)
#define | RCC_I2SPRE_RATIO_427 (0x1A9U << 1)
#define | RCC_I2SPRE_RATIO_428 (0x1AAU << 1)
#define | RCC_I2SPRE_RATIO_429 (0x1ABU << 1)
#define | RCC_I2SPRE_RATIO_430 (0x1ACU << 1)
#define | RCC_I2SPRE_RATIO_431 (0x1ADU << 1)
#define | RCC_I2SPRE_RATIO_432 (0x1AEU << 1)
#define | RCC_I2SPRE_RATIO_433 (0x1AFU << 1)
#define | RCC_I2SPRE_RATIO_434 (0x1B0U << 1)
#define | RCC_I2SPRE_RATIO_435 (0x1B1U << 1)
#define | RCC_I2SPRE_RATIO_436 (0x1B2U << 1)
#define | RCC_I2SPRE_RATIO_437 (0x1B3U << 1)
#define | RCC_I2SPRE_RATIO_438 (0x1B4U << 1)
#define | RCC_I2SPRE_RATIO_439 (0x1B5U << 1)
#define | RCC_I2SPRE_RATIO_440 (0x1B6U << 1)
#define | RCC_I2SPRE_RATIO_441 (0x1B7U << 1)
#define | RCC_I2SPRE_RATIO_442 (0x1B8U << 1)
#define | RCC_I2SPRE_RATIO_443 (0x1B9U << 1)
#define | RCC_I2SPRE_RATIO_444 (0x1BAU << 1)
#define | RCC_I2SPRE_RATIO_445 (0x1BBU << 1)
#define | RCC_I2SPRE_RATIO_446 (0x1BCU << 1)
#define | RCC_I2SPRE_RATIO_447 (0x1BDU << 1)
#define | RCC_I2SPRE_RATIO_448 (0x1BEU << 1)
#define | RCC_I2SPRE_RATIO_449 (0x1BFU << 1)
#define | RCC_I2SPRE_RATIO_450 (0x1C0U << 1)
#define | RCC_I2SPRE_RATIO_451 (0x1C1U << 1)
#define | RCC_I2SPRE_RATIO_452 (0x1C2U << 1)
#define | RCC_I2SPRE_RATIO_453 (0x1C3U << 1)
#define | RCC_I2SPRE_RATIO_454 (0x1C4U << 1)
#define | RCC_I2SPRE_RATIO_455 (0x1C5U << 1)
#define | RCC_I2SPRE_RATIO_456 (0x1C6U << 1)
#define | RCC_I2SPRE_RATIO_457 (0x1C7U << 1)
#define | RCC_I2SPRE_RATIO_458 (0x1C8U << 1)
#define | RCC_I2SPRE_RATIO_459 (0x1C9U << 1)
#define | RCC_I2SPRE_RATIO_460 (0x1CAU << 1)
#define | RCC_I2SPRE_RATIO_461 (0x1CBU << 1)
#define | RCC_I2SPRE_RATIO_462 (0x1CCU << 1)
#define | RCC_I2SPRE_RATIO_463 (0x1CDU << 1)
#define | RCC_I2SPRE_RATIO_464 (0x1CEU << 1)
#define | RCC_I2SPRE_RATIO_465 (0x1CFU << 1)
#define | RCC_I2SPRE_RATIO_466 (0x1D0U << 1)
#define | RCC_I2SPRE_RATIO_467 (0x1D1U << 1)
#define | RCC_I2SPRE_RATIO_468 (0x1D2U << 1)
#define | RCC_I2SPRE_RATIO_469 (0x1D3U << 1)
#define | RCC_I2SPRE_RATIO_470 (0x1D4U << 1)
#define | RCC_I2SPRE_RATIO_471 (0x1D5U << 1)
#define | RCC_I2SPRE_RATIO_472 (0x1D6U << 1)
#define | RCC_I2SPRE_RATIO_473 (0x1D7U << 1)
#define | RCC_I2SPRE_RATIO_474 (0x1D8U << 1)
#define | RCC_I2SPRE_RATIO_475 (0x1D9U << 1)
#define | RCC_I2SPRE_RATIO_476 (0x1DAU << 1)
#define | RCC_I2SPRE_RATIO_477 (0x1DBU << 1)
#define | RCC_I2SPRE_RATIO_478 (0x1DCU << 1)
#define | RCC_I2SPRE_RATIO_479 (0x1DDU << 1)
#define | RCC_I2SPRE_RATIO_480 (0x1DEU << 1)
#define | RCC_I2SPRE_RATIO_481 (0x1DFU << 1)
#define | RCC_I2SPRE_RATIO_482 (0x1E0U << 1)
#define | RCC_I2SPRE_RATIO_483 (0x1E1U << 1)
#define | RCC_I2SPRE_RATIO_484 (0x1E2U << 1)
#define | RCC_I2SPRE_RATIO_485 (0x1E3U << 1)
#define | RCC_I2SPRE_RATIO_486 (0x1E4U << 1)
#define | RCC_I2SPRE_RATIO_487 (0x1E5U << 1)
#define | RCC_I2SPRE_RATIO_488 (0x1E6U << 1)
#define | RCC_I2SPRE_RATIO_489 (0x1E7U << 1)
#define | RCC_I2SPRE_RATIO_490 (0x1E8U << 1)
#define | RCC_I2SPRE_RATIO_491 (0x1E9U << 1)
#define | RCC_I2SPRE_RATIO_492 (0x1EAU << 1)
#define | RCC_I2SPRE_RATIO_493 (0x1EBU << 1)
#define | RCC_I2SPRE_RATIO_494 (0x1ECU << 1)
#define | RCC_I2SPRE_RATIO_495 (0x1EDU << 1)
#define | RCC_I2SPRE_RATIO_496 (0x1EEU << 1)
#define | RCC_I2SPRE_RATIO_497 (0x1EFU << 1)
#define | RCC_I2SPRE_RATIO_498 (0x1F0U << 1)
#define | RCC_I2SPRE_RATIO_499 (0x1F1U << 1)
#define | RCC_I2SPRE_RATIO_500 (0x1F2U << 1)
#define | RCC_I2SPRE_RATIO_501 (0x1F3U << 1)
#define | RCC_I2SPRE_RATIO_502 (0x1F4U << 1)
#define | RCC_I2SPRE_RATIO_503 (0x1F5U << 1)
#define | RCC_I2SPRE_RATIO_504 (0x1F6U << 1)
#define | RCC_I2SPRE_RATIO_505 (0x1F7U << 1)
#define | RCC_I2SPRE_RATIO_506 (0x1F8U << 1)
#define | RCC_I2SPRE_RATIO_507 (0x1F9U << 1)
#define | RCC_I2SPRE_RATIO_508 (0x1FAU << 1)
#define | RCC_I2SPRE_RATIO_509 (0x1FBU << 1)
#define | RCC_I2SPRE_RATIO_510 (0x1FCU << 1)
#define | RCC_I2SPRE_RATIO_511 (0x1FDU << 1)
#define | RCC_I2SPRE_RATIO_512 (0x1FEU << 1)
#define | RCC_I2SPRE_SRCEN (0x1U << 10)
#define | RCC_MCLKSRC_MAINCLK (0x0U)
#define | RCC_MCLKSRC_FHSI (0x1U)
#define | RCC_USBFIFOCLKSRC_AHBCLK (0x0U)
#define | RCC_USBFIFOCLKSRC_USBCLK (0x1U)
#define | RCC_MCOSEL_NOCLOCK (0x0U)
#define | RCC_MCOSEL_AHBCLK (0x1U << 0)
#define | RCC_MCOSEL_HSE (0x1U << 1)
#define | RCC_MCOSEL_MHSI (0x1U << 2)
#define | RCC_MCOSEL_PLLDIV2 (0x1U << 3)
#define | RCC_MCOSEL_MCLK (0x1U << 4)
#define | RCC_AHBENR0_IWDGEN (0x1U << 2)
#define | RCC_AHBENR1_USBEN (0x1U << 1)
#define | RCC_AHBENR1_ISOEN (0x1U << 2)
#define | RCC_AHBENR1_FLASHEN (0x1U << 3)
#define | RCC_AHBENR1_CACHEEN (0x1U << 4)
#define | RCC_AHBENR1_SYSEN (0x1U << 5)
#define | RCC_AHBENR1_DMAC1BREN (0x1U << 6)
#define | RCC_AHBENR1_DMAC2BREN (0x1U << 7)
#define | RCC_AHBENR1_CRCSFMEN (0x1U << 8)
#define | RCC_AHBENR2_BDIEN (0x1U << 2)
#define | RCC_APB1ENR_DMAC1EN (0x1U << 0)
#define | RCC_APB1ENR_TIM1EN (0x1U << 1)
#define | RCC_APB1ENR_TIM2EN (0x1U << 2)
#define | RCC_APB1ENR_TIM3EN (0x1U << 3)
#define | RCC_APB1ENR_TIM4EN (0x1U << 4)
#define | RCC_APB1ENR_GPIOAEN (0x1U << 5)
#define | RCC_APB1ENR_GPIOBEN (0x1U << 6)
#define | RCC_APB1ENR_GPIOCEN (0x1U << 7)
#define | RCC_APB1ENR_GPIODEN (0x1U << 8)
#define | RCC_APB1ENR_EXTIEN (0x1U << 9)
#define | RCC_APB1ENR_AFIOEN (0x1U << 10)
#define | RCC_APB1ENR_ADCEN (0x1U << 11)
#define | RCC_APB1ENR_QSPIEN (0x1U << 12)
#define | RCC_APB1ENR_SPIS1EN (0x1U << 13)
#define | RCC_APB1ENR_UART1EN (0x1U << 14)
#define | RCC_APB1ENR_BMX1EN (0x1U << 15)
#define | RCC_APB2ENR_DMAC2EN (0x1U << 0)
#define | RCC_APB2ENR_WWDGEN (0x1U << 1)
#define | RCC_APB2ENR_UART2EN (0x1U << 2)
#define | RCC_APB2ENR_UART3EN (0x1U << 3)
#define | RCC_APB2ENR_SPIM2EN (0x1U << 4)
#define | RCC_APB2ENR_SPIS2EN (0x1U << 5)
#define | RCC_APB2ENR_I2SEN (0x1U << 6)
#define | RCC_APB2ENR_I2C1EN (0x1U << 7)
#define | RCC_APB2ENR_I2C2EN (0x1U << 8)
#define | RCC_APB2ENR_RNGEN (0x1U << 9)
#define | RCC_APB2ENR_LEDEN (0x1U << 10)
#define | RCC_APB2ENR_BMX2EN (0x1U << 11)
#define | RCC_RNGCLKENR_CLKEN (0x1U)
#define | RCC_IWDGCLKENR_IWDGCLKEN (0x1U)
#define | RCC_IWDGCLKENR_DCSSCLKEN (0x1U << 2)
#define | RCC_USBCLKENR_CLKEN (0x1U)
#define | RCC_I2SCLKENR_CLKEN (0x1U)
#define | RCC_SPIS1CLKENR_CLKEN (0x1U)
#define | RCC_SPIS2CLKENR_CLKEN (0x1U)
#define | RCC_USBFIFOCLKENR_CLKEN (0x1U)
#define | RCC_AHBRSTR1_USBRST (0x1U << 1)
#define | RCC_AHBRSTR1_ISORST (0x1U << 2)
#define | RCC_AHBRSTR1_FLASHRST (0x1U << 3)
#define | RCC_AHBRSTR1_CACHERST (0x1U << 4)
#define | RCC_AHBRSTR1_SYSRST (0x1U << 5)
#define | RCC_AHBRSTR1_CRCSFMRST (0x1U << 8)
#define | RCC_APB1RSTR_DMAC1RST (0x1U << 0)
#define | RCC_APB1RSTR_TIM1RST (0x1U << 1)
#define | RCC_APB1RSTR_TIM2RST (0x1U << 2)
#define | RCC_APB1RSTR_TIM3RST (0x1U << 3)
#define | RCC_APB1RSTR_TIM4RST (0x1U << 4)
#define | RCC_APB1RSTR_GPIOARST (0x1U << 5)
#define | RCC_APB1RSTR_GPIOBRST (0x1U << 6)
#define | RCC_APB1RSTR_GPIOCRST (0x1U << 7)
#define | RCC_APB1RSTR_GPIODRST (0x1U << 8)
#define | RCC_APB1RSTR_EXTIRST (0x1U << 9)
#define | RCC_APB1RSTR_AFIORST (0x1U << 10)
#define | RCC_APB1RSTR_ADCRST (0x1U << 11)
#define | RCC_APB1RSTR_QSPIRST (0x1U << 12)
#define | RCC_APB1RSTR_SPIS1RST (0x1U << 13)
#define | RCC_APB1RSTR_UART1RST (0x1U << 14)
#define | RCC_APB1RSTR_BMX1RST (0x1U << 15)
#define | RCC_APB2RSTR_DMAC2RST (0x1U << 0)
#define | RCC_APB2RSTR_WWDGRST (0x1U << 1)
#define | RCC_APB2RSTR_UART2RST (0x1U << 2)
#define | RCC_APB2RSTR_UART3RST (0x1U << 3)
#define | RCC_APB2RSTR_SPIM2RST (0x1U << 4)
#define | RCC_APB2RSTR_SPIS2RST (0x1U << 5)
#define | RCC_APB2RSTR_I2SRST (0x1U << 6)
#define | RCC_APB2RSTR_I2C1RST (0x1U << 7)
#define | RCC_APB2RSTR_I2C2RST (0x1U << 8)
#define | RCC_APB2RSTR_RNGRST (0x1U << 9)
#define | RCC_APB2RSTR_LEDRST (0x1U << 10)
#define | RCC_APB2RSTR_BMX2RST (0x1U << 11)
#define | RCC_I2SCLKRSTR_SCLKRST (0x1U)
#define | RCC_CLRRSTSTAT_CLR (0x1U)
#define | RCC_BDRSTR_BDRST (0x1U)
#define | RCC_LSI2RTCENR_CLKEN (0x1U)
#define | RCC_HSE2RTCENR_DIVEN (0x1U)
#define | RCC_RSTSTAT_LPWRRSTF (0x1U << 0)
#define | RCC_RSTSTAT_WWDGRSTF (0x1U << 1)
#define | RCC_RSTSTAT_IWDGRSTF (0x1U << 2)
#define | RCC_RSTSTAT_SFTRSTF (0x1U << 3)
#define | RCC_RSTSTAT_PORRSTF (0x1U << 4)
#define | RCC_RSTSTAT_PINRSTF (0x1U << 5)
#define | PWR_CR0_DBP (0x1U << 0)
#define | PWR_CR0_FCLKSD (0x1U << 3)
#define | PWR_CR0_PDDS_Pos (5U)
#define | PWR_CR0_PDDS_Msk (0x3U << PWR_CR0_PDDS_Pos)
#define | PWR_CR0_S32KMODE (0x1U << 18)
#define | PWR_CR0_S4KMODE (0x1U << 19)
#define | PWR_CR1_CWUF (0x1U << 0)
#define | PWR_CR1_CSBF (0x1U << 1)
#define | PWR_CR1_CSPF (0x1U << 2)
#define | PWR_CR1_CCKF (0x1U << 3)
#define | PWR_CR2_EWUP (0x1U << 0)
#define | PWR_SR0_PVDO (0x1U << 0)
#define | PWR_SR1_WUF (0x1U << 0)
#define | PWR_SR1_SBF (0x1U << 1)
#define | PWR_SR1_SPF (0x1U << 2)
#define | PWR_SR1_CKF (0x1U << 3)
#define | BIT_BAND_ADDR(addr, bitnum) ((((uint32_t)(addr)) & 0xF0000000) + 0x2000000 + ((((uint32_t)(addr)) & 0xFFFFF) << 5) + ((bitnum) << 2))

## 类型定义
typedef enum IRQn | IRQn_Type
typedef enum FlagStatus | ITStatus

## 枚举
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FMC_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMAC1_IRQn = 11, DMAC2_IRQn = 12, ADC_IRQn = 13, USB_IRQn = 14, USB_DMA_IRQn = 15, EXTI9_5_IRQn = 16, TIM1_BRK_IRQn = 17, TIM1_UP_IRQn = 18, TIM1_TRG_COM_IRQn = 19, TIM1_CC_IRQn = 20, TIM2_IRQn = 21, TIM3_IRQn = 22, TIM4_IRQn = 23, I2C1_IRQn = 24, I2C2_IRQn = 25, QSPI_IRQn = 26, SPIM2_IRQn = 27, SPIS1_IRQn = 28, SPIS2_IRQn = 29, UART1_IRQn = 30, UART2_IRQn = 31, UART3_IRQn = 32, EXTI15_10_IRQn = 33, RTCAlarm_IRQn = 34, USBP_WKUP_IRQn = 35, I2S_IRQn = 36, ISO_IRQn = 37 }
enum | FlagStatus { RESET = 0, SET = !RESET }
enum | FunctionalState { DISABLE = 0, ENABLE = !DISABLE }
enum | SignalState { INACTIVE = 0, ACTIVE = !INACTIVE }
enum | ErrorStatus { ERROR = 0, SUCCESS = !ERROR }

## 详细描述

## 宏定义说明

## ◆ ADC_CR1_AWDCH

#define ADC_CR1_AWDCH ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

## ◆ ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)

Bit 3

## ◆ ADC_CR1_AWDCH_4

#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)

Bit 4

## ◆ ADC_CR1_AWDEN

#define ADC_CR1_AWDEN ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

## ◆ ADC_CR1_AWDIE

#define ADC_CR1_AWDIE ((uint32_t)0x00000040)

Analog Watchdog interrupt enable

## ◆ ADC_CR1_AWDSGL

#define ADC_CR1_AWDSGL ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

## ◆ ADC_CR1_DISCEN

#define ADC_CR1_DISCEN ((uint32_t)0x00000800)

Discontinuous mode on regular channels

## ◆ ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

## ◆ ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)

Bit 0

## ◆ ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)

Bit 1

## ◆ ADC_CR1_DISCNUM_2

#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)

Bit 2

## ◆ ADC_CR1_EOCIE

#define ADC_CR1_EOCIE ((uint32_t)0x00000020)

Interrupt enable for EOC

## ◆ ADC_CR1_JAUTO

#define ADC_CR1_JAUTO ((uint32_t)0x00000400)

Automatic injected group conversion

## ◆ ADC_CR1_JAWDEN

#define ADC_CR1_JAWDEN ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

## ◆ ADC_CR1_JDISCEN

#define ADC_CR1_JDISCEN ((uint32_t)0x00001000)

Discontinuous mode on injected channels

## ◆ ADC_CR1_JEOCIE

#define ADC_CR1_JEOCIE ((uint32_t)0x00000080)

Interrupt enable for injected channels

## ◆ ADC_CR1_SCAN

#define ADC_CR1_SCAN ((uint32_t)0x00000100)

Scan mode

## ◆ ADC_CR2_ADON

#define ADC_CR2_ADON ((uint32_t)0x00000001)

A/D Converter ON / OFF

## ◆ ADC_CR2_ALIGN

#define ADC_CR2_ALIGN ((uint32_t)0x00000800)

Data Alignment

## ◆ ADC_CR2_CAL

#define ADC_CR2_CAL ((uint32_t)0x00000004)

A/D Calibration

## ◆ ADC_CR2_CONT

#define ADC_CR2_CONT ((uint32_t)0x00000002)

Continuous Conversion

## ◆ ADC_CR2_DMAEN

#define ADC_CR2_DMAEN ((uint32_t)0x00000100)

XXXXX

## ◆ ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000)

EXTSEL[2:0] bits (External Event Select for regular group)

## ◆ ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000)

Bit 0

## ◆ ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000)

Bit 1

## ◆ ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000)

Bit 2

## ◆ ADC_CR2_EXTSYNC

#define ADC_CR2_EXTSYNC ((uint32_t)0x00010000)

XXXXX

## ◆ ADC_CR2_EXTTRIG

#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000)

External Trigger Conversion mode for regular channels

## ◆ ADC_CR2_JDMAEN

#define ADC_CR2_JDMAEN ((uint32_t)0x00000200)

XXXXX

## ◆ ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000)

JEXTSEL[2:0] bits (External event select for injected group)

## ◆ ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000)

Bit 0

## ◆ ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000)

Bit 1

## ◆ ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000)

Bit 2

## ◆ ADC_CR2_JEXTSYNC

#define ADC_CR2_JEXTSYNC ((uint32_t)0x00000400)

XXXXX

## ◆ ADC_CR2_JEXTTRIG

#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000)

External Trigger Conversion mode for injected channels

## ◆ ADC_CR2_JSWSTART

#define ADC_CR2_JSWSTART ((uint32_t)0x00200000)

Start Conversion of injected channels

## ◆ ADC_CR2_RSTCAL

#define ADC_CR2_RSTCAL ((uint32_t)0x00000008)

Reset Calibration

## ◆ ADC_CR2_SWSTART

#define ADC_CR2_SWSTART ((uint32_t)0x00400000)

Start Conversion of regular channels

## ◆ ADC_CR2_TSVREFE

#define ADC_CR2_TSVREFE ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

## ◆ ADC_CR3_12BIT

#define ADC_CR3_12BIT ((uint32_t)0x00000040)

12-bit enable

## ◆ ADC_CR3_ADVMODE

#define ADC_CR3_ADVMODE ((uint32_t)0x00000003)

ADVMODE[1:0] bits

## ◆ ADC_CR3_EMPIE

#define ADC_CR3_EMPIE ((uint32_t)0x00020000)

ADC fifo empty interrupt enable

## ◆ ADC_CR3_OVFIE

#define ADC_CR3_OVFIE ((uint32_t)0x00010000)

ADC fifo overflow interrupt enable

## ◆ ADC_CR3_PRS

#define ADC_CR3_PRS ((uint32_t)0x0000FF00)

PRS[7:0] bits (Prescaler to the apb clock input)

## ◆ ADC_CR3_SAMCHN

#define ADC_CR3_SAMCHN ((uint32_t)0x0000000C)

SAMCHN[1:0] bits

## ◆ ADC_CR3_VREFCFG

#define ADC_CR3_VREFCFG ((uint32_t)0x00000030)

VREFCFG[1:0] bits

## ◆ ADC_DR_DATA

#define ADC_DR_DATA ((uint32_t)0x0000FFFF)

Regular data

## ◆ ADC_HTR_HT

#define ADC_HTR_HT ((uint16_t)0x0FFF)

Analog watchdog high threshold

## ◆ ADC_JDMAR_JDATA

#define ADC_JDMAR_JDATA ((uint16_t)0xFFFF)

Injected data

## ◆ ADC_JDR1_JDATA

#define ADC_JDR1_JDATA ((uint16_t)0xFFFF)

Injected data

## ◆ ADC_JDR2_JDATA

#define ADC_JDR2_JDATA ((uint16_t)0xFFFF)

Injected data

## ◆ ADC_JDR3_JDATA

#define ADC_JDR3_JDATA ((uint16_t)0xFFFF)

Injected data

## ◆ ADC_JDR4_JDATA

#define ADC_JDR4_JDATA ((uint16_t)0xFFFF)

Injected data

## ◆ ADC_JOFR1_JOFFSET1

#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)

Data offset for injected channel 1

## ◆ ADC_JOFR2_JOFFSET2

#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)

Data offset for injected channel 2

## ◆ ADC_JOFR3_JOFFSET3

#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)

Data offset for injected channel 3

## ◆ ADC_JOFR4_JOFFSET4

#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)

Data offset for injected channel 4

## ◆ ADC_JSQR_JL

#define ADC_JSQR_JL ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

## ◆ ADC_JSQR_JL_0

#define ADC_JSQR_JL_0 ((uint32_t)0x00100000)

Bit 0

## ◆ ADC_JSQR_JL_1

#define ADC_JSQR_JL_1 ((uint32_t)0x00200000)

Bit 1

## ◆ ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

## ◆ ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)

Bit 3

## ◆ ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)

Bit 4

## ◆ ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

## ◆ ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)

Bit 0

## ◆ ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)

Bit 1

## ◆ ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)

Bit 2

## ◆ ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)

Bit 3

## ◆ ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)

Bit 4

## ◆ ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

## ◆ ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)

Bit 0

## ◆ ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)

Bit 1

## ◆ ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)

Bit 2

## ◆ ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)

Bit 3

## ◆ ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)

Bit 4

## ◆ ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

## ◆ ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)

Bit 0

## ◆ ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)

Bit 1

## ◆ ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)

Bit 2

## ◆ ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)

Bit 3

## ◆ ADC_JSQR_JSQ4_4

#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)

Bit 4

## ◆ ADC_LTR_LT

#define ADC_LTR_LT ((uint16_t)0x0FFF)

Analog watchdog low threshold

## ◆ ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

## ◆ ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

## ◆ ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)

Bit 0

## ◆ ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)

Bit 1

## ◆ ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)

Bit 2

## ◆ ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

## ◆ ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)

Bit 0

## ◆ ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)

Bit 1

## ◆ ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)

Bit 2

## ◆ ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

## ◆ ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)

Bit 0

## ◆ ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)

Bit 1

## ◆ ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)

Bit 2

## ◆ ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

## ◆ ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)

Bit 0

## ◆ ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)

Bit 1

## ◆ ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)

Bit 2

## ◆ ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 15 Sample time selection)

## ◆ ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)

Bit 0

## ◆ ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)

Bit 1

## ◆ ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)

Bit 2

## ◆ ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

## ◆ ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)

Bit 0

## ◆ ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)

Bit 1

## ◆ ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)

Bit 2

## ◆ ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

## ◆ ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)

Bit 0

## ◆ ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)

Bit 1

## ◆ ADC_SMPR1_SMP17_2

#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)

Bit 2

## ◆ ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

## ◆ ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

## ◆ ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)

Bit 0

## ◆ ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)

Bit 1

## ◆ ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)

Bit 2

## ◆ ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

## ◆ ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)

Bit 0

## ◆ ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)

Bit 1

## ◆ ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)

Bit 2

## ◆ ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

## ◆ ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)

Bit 0

## ◆ ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)

Bit 1

## ◆ ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)

Bit 2

## ◆ ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

## ◆ ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)

Bit 0

## ◆ ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)

Bit 1

## ◆ ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)

Bit 2

## ◆ ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

## ◆ ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)

Bit 0

## ◆ ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)

Bit 1

## ◆ ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)

Bit 2

## ◆ ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

## ◆ ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)

Bit 0

## ◆ ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)

Bit 1

## ◆ ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)

Bit 2

## ◆ ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

## ◆ ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)

Bit 0

## ◆ ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)

Bit 1

## ◆ ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)

Bit 2

## ◆ ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

## ◆ ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)

Bit 0

## ◆ ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)

Bit 1

## ◆ ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)

Bit 2

## ◆ ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

## ◆ ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)

Bit 0

## ◆ ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)

Bit 1

## ◆ ADC_SMPR2_SMP9_2

#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)

Bit 2

## ◆ ADC_SQR1_L

#define ADC_SQR1_L ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

## ◆ ADC_SQR1_L_0

#define ADC_SQR1_L_0 ((uint32_t)0x00100000)

Bit 0

## ◆ ADC_SQR1_L_1

#define ADC_SQR1_L_1 ((uint32_t)0x00200000)

Bit 1

## ◆ ADC_SQR1_L_2

#define ADC_SQR1_L_2 ((uint32_t)0x00400000)

Bit 2

## ◆ ADC_SQR1_L_3

#define ADC_SQR1_L_3 ((uint32_t)0x00800000)

Bit 3

## ◆ ADC_SQR1_SQ13

#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

## ◆ ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)

Bit 3

## ◆ ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)

Bit 4

## ◆ ADC_SQR1_SQ14

#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

## ◆ ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)

Bit 0

## ◆ ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)

Bit 1

## ◆ ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)

Bit 2

## ◆ ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)

Bit 3

## ◆ ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)

Bit 4

## ◆ ADC_SQR1_SQ15

#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

## ◆ ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)

Bit 0

## ◆ ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)

Bit 1

## ◆ ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)

Bit 2

## ◆ ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)

Bit 3

## ◆ ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)

Bit 4

## ◆ ADC_SQR1_SQ16

#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

## ◆ ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)

Bit 0

## ◆ ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)

Bit 1

## ◆ ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)

Bit 2

## ◆ ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)

Bit 3

## ◆ ADC_SQR1_SQ16_4

#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)

Bit 4

## ◆ ADC_SQR2_SQ10

#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

## ◆ ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)

Bit 0

## ◆ ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)

Bit 1

## ◆ ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)

Bit 2

## ◆ ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)

Bit 3

## ◆ ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)

Bit 4

## ◆ ADC_SQR2_SQ11

#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

## ◆ ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)

Bit 0

## ◆ ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)

Bit 1

## ◆ ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)

Bit 2

## ◆ ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)

Bit 3

## ◆ ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)

Bit 4

## ◆ ADC_SQR2_SQ12

#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

## ◆ ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)

Bit 0

## ◆ ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)

Bit 1

## ◆ ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)

Bit 2

## ◆ ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)

Bit 3

## ◆ ADC_SQR2_SQ12_4

#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)

Bit 4

## ◆ ADC_SQR2_SQ7

#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

## ◆ ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)

Bit 3

## ◆ ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)

Bit 4

## ◆ ADC_SQR2_SQ8

#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

## ◆ ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)

Bit 0

## ◆ ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)

Bit 1

## ◆ ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)

Bit 2

## ◆ ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)

Bit 3

## ◆ ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)

Bit 4

## ◆ ADC_SQR2_SQ9

#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

## ◆ ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)

Bit 0

## ◆ ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)

Bit 1

## ◆ ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)

Bit 2

## ◆ ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)

Bit 3

## ◆ ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)

Bit 4

## ◆ ADC_SQR3_SQ1

#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

## ◆ ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)

Bit 0

## ◆ ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)

Bit 1

## ◆ ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)

Bit 2

## ◆ ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)

Bit 3

## ◆ ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)

Bit 4

## ◆ ADC_SQR3_SQ2

#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

## ◆ ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)

Bit 0

## ◆ ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)

Bit 1

## ◆ ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)

Bit 2

## ◆ ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)

Bit 3

## ◆ ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)

Bit 4

## ◆ ADC_SQR3_SQ3

#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

## ◆ ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)

Bit 0

## ◆ ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)

Bit 1

## ◆ ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)

Bit 2

## ◆ ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)

Bit 3

## ◆ ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)

Bit 4

## ◆ ADC_SQR3_SQ4

#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

## ◆ ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)

Bit 0

## ◆ ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)

Bit 1

## ◆ ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)

Bit 2

## ◆ ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)

Bit 3

## ◆ ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)

Bit 4

## ◆ ADC_SQR3_SQ5

#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

## ◆ ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)

Bit 0

## ◆ ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)

Bit 1

## ◆ ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)

Bit 2

## ◆ ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)

Bit 3

## ◆ ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)

Bit 4

## ◆ ADC_SQR3_SQ6

#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

## ◆ ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)

Bit 0

## ◆ ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)

Bit 1

## ◆ ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)

Bit 2

## ◆ ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)

Bit 3

## ◆ ADC_SQR3_SQ6_4

#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)

Bit 4

## ◆ ADC_SR_AWD

#define ADC_SR_AWD ((uint8_t)0x01)

Analog watchdog flag

## ◆ ADC_SR_EMP

#define ADC_SR_EMP ((uint8_t)0x20)

XXXXX flag

## ◆ ADC_SR_EOC

#define ADC_SR_EOC ((uint8_t)0x02)

End of conversion

## ◆ ADC_SR_JEOC

#define ADC_SR_JEOC ((uint8_t)0x04)

Injected channel end of conversion

## ◆ ADC_SR_JSTRT

#define ADC_SR_JSTRT ((uint8_t)0x08)

Injected channel Start flag

## ◆ ADC_SR_OVF

#define ADC_SR_OVF ((uint8_t)0x40)

XXXXX flag

## ◆ ADC_SR_STRT

#define ADC_SR_STRT ((uint8_t)0x10)

Regular channel Start flag

## ◆ AFIO_EXTICR1_EXTI0_Msk

#define AFIO_EXTICR1_EXTI0_Msk ((uint16_t)0x000F)

EXTI 0 configuration

## ◆ AFIO_EXTICR1_EXTI0_PA

#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000)

PA[0] pin

## ◆ AFIO_EXTICR1_EXTI0_PB

#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001)

PB[0] pin

## ◆ AFIO_EXTICR1_EXTI0_PC

#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002)

PC[0] pin

## ◆ AFIO_EXTICR1_EXTI0_PD

#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003)

PD[0] pin EXTI1 configuration

## ◆ AFIO_EXTICR1_EXTI1_Msk

#define AFIO_EXTICR1_EXTI1_Msk ((uint16_t)0x00F0)

EXTI 1 configuration

## ◆ AFIO_EXTICR1_EXTI1_PA

#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000)

PA[1] pin

## ◆ AFIO_EXTICR1_EXTI1_PB

#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010)

PB[1] pin

## ◆ AFIO_EXTICR1_EXTI1_PC

#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020)

PC[1] pin

## ◆ AFIO_EXTICR1_EXTI1_PD

#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030)

PD[1] pin EXTI2 configuration

## ◆ AFIO_EXTICR1_EXTI2_Msk

#define AFIO_EXTICR1_EXTI2_Msk ((uint16_t)0x0F00)

EXTI 2 configuration

## ◆ AFIO_EXTICR1_EXTI2_PA

#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000)

PA[2] pin

## ◆ AFIO_EXTICR1_EXTI2_PB

#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100)

PB[2] pin

## ◆ AFIO_EXTICR1_EXTI2_PC

#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200)

PC[2] pin

## ◆ AFIO_EXTICR1_EXTI2_PD

#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300)

PD[2] pin EXTI3 configuration

## ◆ AFIO_EXTICR1_EXTI3_Msk

#define AFIO_EXTICR1_EXTI3_Msk ((uint16_t)0xF000)

EXTI 3 configuration EXTI0 configuration

## ◆ AFIO_EXTICR1_EXTI3_PA

#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000)

PA[3] pin

## ◆ AFIO_EXTICR1_EXTI3_PB

#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000)

PB[3] pin

## ◆ AFIO_EXTICR1_EXTI3_PC

#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000)

PC[3] pin

## ◆ AFIO_EXTICR2_EXTI4_Msk

#define AFIO_EXTICR2_EXTI4_Msk ((uint16_t)0x000F)

EXTI 4 configuration

## ◆ AFIO_EXTICR2_EXTI4_PA

#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000)

PA[4] pin

## ◆ AFIO_EXTICR2_EXTI4_PB

#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001)

PB[4] pin

## ◆ AFIO_EXTICR2_EXTI4_PC

#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002)

PC[4] pin EXTI5 configuration

## ◆ AFIO_EXTICR2_EXTI5_Msk

#define AFIO_EXTICR2_EXTI5_Msk ((uint16_t)0x00F0)

EXTI 5 configuration

## ◆ AFIO_EXTICR2_EXTI5_PA

#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000)

PA[5] pin

## ◆ AFIO_EXTICR2_EXTI5_PB

#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010)

PB[5] pin

## ◆ AFIO_EXTICR2_EXTI5_PC

#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020)

PC[5] pin EXTI6 configuration

## ◆ AFIO_EXTICR2_EXTI6_Msk

#define AFIO_EXTICR2_EXTI6_Msk ((uint16_t)0x0F00)

EXTI 6 configuration

## ◆ AFIO_EXTICR2_EXTI6_PA

#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000)

PA[6] pin

## ◆ AFIO_EXTICR2_EXTI6_PB

#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100)

PB[6] pin

## ◆ AFIO_EXTICR2_EXTI6_PC

#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200)

PC[6] pin EXTI7 configuration

## ◆ AFIO_EXTICR2_EXTI7_Msk

#define AFIO_EXTICR2_EXTI7_Msk ((uint16_t)0xF000)

EXTI 7 configuration EXTI4 configuration

## ◆ AFIO_EXTICR2_EXTI7_PA

#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000)

PA[7] pin

## ◆ AFIO_EXTICR2_EXTI7_PB

#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000)

PB[7] pin

## ◆ AFIO_EXTICR2_EXTI7_PC

#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000)

PC[7] pin

## ◆ AFIO_EXTICR3_EXTI10_Msk

#define AFIO_EXTICR3_EXTI10_Msk ((uint16_t)0x0F00)

EXTI 10 configuration

## ◆ AFIO_EXTICR3_EXTI10_PA

#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000)

PA[10] pin

## ◆ AFIO_EXTICR3_EXTI10_PB

#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100)

PB[10] pin

## ◆ AFIO_EXTICR3_EXTI10_PC

#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200)

PC[10] pin EXTI11 configuration

## ◆ AFIO_EXTICR3_EXTI11_Msk

#define AFIO_EXTICR3_EXTI11_Msk ((uint16_t)0xF000)

EXTI 11 configuration EXTI8 configuration

## ◆ AFIO_EXTICR3_EXTI11_PA

#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000)

PA[11] pin

## ◆ AFIO_EXTICR3_EXTI11_PB

#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000)

PB[11] pin

## ◆ AFIO_EXTICR3_EXTI11_PC

#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000)

PC[11] pin

## ◆ AFIO_EXTICR3_EXTI8_Msk

#define AFIO_EXTICR3_EXTI8_Msk ((uint16_t)0x000F)

EXTI 8 configuration

## ◆ AFIO_EXTICR3_EXTI8_PA

#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000)

PA[8] pin

## ◆ AFIO_EXTICR3_EXTI8_PB

#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001)

PB[8] pin

## ◆ AFIO_EXTICR3_EXTI8_PC

#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002)

PC[8] pin EXTI9 configuration

## ◆ AFIO_EXTICR3_EXTI9_Msk

#define AFIO_EXTICR3_EXTI9_Msk ((uint16_t)0x00F0)

EXTI 9 configuration

## ◆ AFIO_EXTICR3_EXTI9_PA

#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000)

PA[9] pin

## ◆ AFIO_EXTICR3_EXTI9_PB

#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010)

PB[9] pin

## ◆ AFIO_EXTICR3_EXTI9_PC

#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020)

PC[9] pin EXTI10 configuration

## ◆ AFIO_EXTICR4_EXTI12_Msk

#define AFIO_EXTICR4_EXTI12_Msk ((uint16_t)0x000F)

EXTI 12 configuration

## ◆ AFIO_EXTICR4_EXTI12_PA

#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000)

PA[12] pin

## ◆ AFIO_EXTICR4_EXTI12_PB

#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)

PB[12] pin

## ◆ AFIO_EXTICR4_EXTI12_PC

#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002)

PC[12] pin

## ◆ AFIO_EXTICR4_EXTI13_Msk

#define AFIO_EXTICR4_EXTI13_Msk ((uint16_t)0x00F0)

EXTI 13 configuration

## ◆ AFIO_EXTICR4_EXTI13_PA

#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000)

PA[13] pin

## ◆ AFIO_EXTICR4_EXTI13_PB

#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010)

PB[13] pin

## ◆ AFIO_EXTICR4_EXTI13_PC

#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020)

PC[13] pin EXTI14 configuration

## ◆ AFIO_EXTICR4_EXTI14_Msk

#define AFIO_EXTICR4_EXTI14_Msk ((uint16_t)0x0F00)

EXTI 14 configuration

## ◆ AFIO_EXTICR4_EXTI14_PA

#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000)

PA[14] pin

## ◆ AFIO_EXTICR4_EXTI14_PB

#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100)

PB[14] pin

## ◆ AFIO_EXTICR4_EXTI14_PC

#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200)

PC[14] pin EXTI15 configuration

## ◆ AFIO_EXTICR4_EXTI15_Msk

#define AFIO_EXTICR4_EXTI15_Msk ((uint16_t)0xF000)

EXTI 15 configuration

## ◆ AFIO_EXTICR4_EXTI15_PA

#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000)

PA[15] pin

## ◆ AFIO_EXTICR4_EXTI15_PB

#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000)

PB[15] pin

## ◆ AFIO_EXTICR4_EXTI15_PC

#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000)

PC[15] pin

## ◆ ANCTL_FHSIENR_FHSION

#define ANCTL_FHSIENR_FHSION (0x1U << 0)

Internal 48M high-speed clock enable

## ◆ ANCTL_FHSISR_FHSIRDY

#define ANCTL_FHSISR_FHSIRDY (0x1U << 0)

Internal 48M high-speed clock ready flag

## ◆ ANCTL_HSESR_HSERDY

#define ANCTL_HSESR_HSERDY (0x1U << 0)

External high-speed clock ready flag

## ◆ ANCTL_LSIENR_LSION

#define ANCTL_LSIENR_LSION (0x1U << 0)

Internal low-speed oscillator enable

## ◆ ANCTL_LSISR_LSIRDY

#define ANCTL_LSISR_LSIRDY (0x1U << 0)

Internal low-speed oscillator ready flag

## ◆ ANCTL_MHSIENR_MHSION

#define ANCTL_MHSIENR_MHSION (0x1U << 0)

Internal 8M high-speed clock enable

## ◆ ANCTL_MHSISR_MHSIRDY

#define ANCTL_MHSISR_MHSIRDY (0x1U << 0)

Internal 8M high-speed clock ready flag

## ◆ ANCTL_PLLENR_PLLON

#define ANCTL_PLLENR_PLLON (0x1U << 0)

PLL enable

## ◆ ANCTL_PVDENR_PVDE

#define ANCTL_PVDENR_PVDE (0x1U << 0)

PVD enable

## ◆ ANCTL_SARENR_SAREN

#define ANCTL_SARENR_SAREN (0x1U << 0)

SAR ADC enable

## ◆ ANCTL_USBPCR_USBPEN

#define ANCTL_USBPCR_USBPEN (0x1U << 0)

USB PHY enable

## ◆ BKP_CR_TPAL

#define BKP_CR_TPAL ((uint8_t)0x02)

TAMPER pin active level

## ◆ BKP_CR_TPE

#define BKP_CR_TPE ((uint8_t)0x01)

TAMPER pin enable

## ◆ BKP_CSR_CTE

#define BKP_CSR_CTE ((uint16_t)0x0001)

Clear Tamper event

## ◆ BKP_CSR_CTI

#define BKP_CSR_CTI ((uint16_t)0x0002)

Clear Tamper Interrupt

## ◆ BKP_CSR_TEF

#define BKP_CSR_TEF ((uint16_t)0x0100)

Tamper Event Flag

## ◆ BKP_CSR_TIF

#define BKP_CSR_TIF ((uint16_t)0x0200)

Tamper Interrupt Flag

## ◆ BKP_CSR_TPIE

#define BKP_CSR_TPIE ((uint16_t)0x0004)

TAMPER Pin interrupt enable

## ◆ BKP_RTCCR_ASOE

#define BKP_RTCCR_ASOE ((uint16_t)0x0100)

Alarm or Second Output Enable

## ◆ BKP_RTCCR_ASOS

#define BKP_RTCCR_ASOS ((uint16_t)0x0200)

Alarm or Second Output Selection

## ◆ BKP_RTCCR_CAL

#define BKP_RTCCR_CAL ((uint16_t)0x007F)

Calibration value

## ◆ BKP_RTCCR_CCO

#define BKP_RTCCR_CCO ((uint16_t)0x0080)

Calibration Clock Output

## ◆ CRC_MODE_BIT_RVS_SUM

#define CRC_MODE_BIT_RVS_SUM (0x1U << 4)

Select bit order revers for CRC_SUM

## ◆ CRC_MODE_BIT_RVS_WR

#define CRC_MODE_BIT_RVS_WR (0x1U << 2)

Select bit order for CRC_WR_DATA

## ◆ CRC_MODE_CMPL_SUM

#define CRC_MODE_CMPL_SUM (0x1U << 5)

Select one's complement for CRC_SUM

## ◆ CRC_MODE_CMPL_WR

#define CRC_MODE_CMPL_WR (0x1U << 3)

Select one's complement for CRC_WR_DATA

## ◆ CRC_MODE_CRC_POLY_CCITT

#define CRC_MODE_CRC_POLY_CCITT (0x1U << 0)

CRC-CCITT polynomial

## ◆ CRC_MODE_CRC_POLY_CRC16

#define CRC_MODE_CRC_POLY_CRC16 (0x2U << 0)

CRC-CRC16 polynomial

## ◆ CRC_MODE_CRC_POLY_CRC32

#define CRC_MODE_CRC_POLY_CRC32 (0x3U << 0)

CRC-CRC32 polynomial

## ◆ CRC_MODE_CRC_POLY_CRC8

#define CRC_MODE_CRC_POLY_CRC8 (0x0U << 0)

CRC-8 polynomial

## ◆ CRC_MODE_CRC_POLY_Msk

#define CRC_MODE_CRC_POLY_Msk (0x3U << 0)

CRC polynomial field mask bit

## ◆ CRC_MODE_SEED_OP

#define CRC_MODE_SEED_OP (0x1U << 6)

CRC seed option set

## ◆ CRC_MODE_SEED_SET

#define CRC_MODE_SEED_SET (0x1U << 7)

Load seed to CRC generator

## ◆ DMAC_CFGH_DEST_PER_Msk

#define DMAC_CFGH_DEST_PER_Msk (0xFU << 11)

No description

## ◆ DMAC_CFGH_DS_UPD_EN

#define DMAC_CFGH_DS_UPD_EN (0x1U << 5)

Destination Status Update Enable

## ◆ DMAC_CFGH_FIFO_MODE

#define DMAC_CFGH_FIFO_MODE (0x1U << 1)

FIFO Mode Select

## ◆ DMAC_CFGH_SRC_PER_Msk

#define DMAC_CFGH_SRC_PER_Msk (0xFU << 7)

No description

## ◆ DMAC_CFGH_SS_UPD_EN

#define DMAC_CFGH_SS_UPD_EN (0x1U << 6)

Source Status Update Enable

## ◆ DMAC_CFGL_CH_PRIOR_Msk

#define DMAC_CFGL_CH_PRIOR_Msk (0x7U << 5)

Channel priority field mask

## ◆ DMAC_CFGL_CH_SUSP

#define DMAC_CFGL_CH_SUSP (0x1U << 8)

Channel Suspend

## ◆ DMAC_CFGL_DST_HS_POL

#define DMAC_CFGL_DST_HS_POL (0x1U << 18)

Destination Handshaking Interface Polarity

## ◆ DMAC_CFGL_FIFO_EMPTY

#define DMAC_CFGL_FIFO_EMPTY (0x1U << 9)

Indicates if there is data left in the channel FIFO

## ◆ DMAC_CFGL_HS_SEL_DST

#define DMAC_CFGL_HS_SEL_DST (0x1U << 10)

Destination Software or Hardware Handshaking Select

## ◆ DMAC_CFGL_HS_SEL_SRC

#define DMAC_CFGL_HS_SEL_SRC (0x1U << 11)

Source Software or Hardware Handshaking Select

## ◆ DMAC_CFGL_RELOAD_DST

#define DMAC_CFGL_RELOAD_DST (0x1U << 31)

Automatic Destination Reload

## ◆ DMAC_CFGL_RELOAD_SRC

#define DMAC_CFGL_RELOAD_SRC (0x1U << 30)

Automatic Source Reload

## ◆ DMAC_CFGL_SRC_HS_POL

#define DMAC_CFGL_SRC_HS_POL (0x1U << 19)

Source Handshaking Interface Polarity

## ◆ DMAC_CTLH_BLOCK_TS_Msk

#define DMAC_CTLH_BLOCK_TS_Msk (0xFFFU)

Block Transfer Size field mask bit

## ◆ DMAC_CTLH_DONE

#define DMAC_CTLH_DONE (0x1U << 12)

Done bit

## ◆ DMAC_CTLL_DEST_MSIZE_1

#define DMAC_CTLL_DEST_MSIZE_1 (0x0U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_128

#define DMAC_CTLL_DEST_MSIZE_128 (0x6U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_16

#define DMAC_CTLL_DEST_MSIZE_16 (0x3U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_256

#define DMAC_CTLL_DEST_MSIZE_256 (0x7U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_32

#define DMAC_CTLL_DEST_MSIZE_32 (0x4U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_4

#define DMAC_CTLL_DEST_MSIZE_4 (0x1U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_64

#define DMAC_CTLL_DEST_MSIZE_64 (0x5U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_8

#define DMAC_CTLL_DEST_MSIZE_8 (0x2U << 11)

Destination Burst Transaction Length

## ◆ DMAC_CTLL_DEST_MSIZE_Msk

#define DMAC_CTLL_DEST_MSIZE_Msk (0x7U << 11)

Destination Burst Transaction Length field mask bit

## ◆ DMAC_CTLL_DINC_DEC

#define DMAC_CTLL_DINC_DEC (0x1U << 7)

Destination Address Increment is decrement

## ◆ DMAC_CTLL_DINC_INC

#define DMAC_CTLL_DINC_INC (0x0U << 7)

Destination Address Increment is increment

## ◆ DMAC_CTLL_DINC_Msk

#define DMAC_CTLL_DINC_Msk (0x3U << 7)

Destination Address Increment field mask bit

## ◆ DMAC_CTLL_DINC_NO

#define DMAC_CTLL_DINC_NO (0x2U << 7)

Destination Address Increment is no change

## ◆ DMAC_CTLL_DST_SCATTER_EN

#define DMAC_CTLL_DST_SCATTER_EN (0x1U << 18)

Destination scatter enable bit

## ◆ DMAC_CTLL_DST_TR_WIDTH_16

#define DMAC_CTLL_DST_TR_WIDTH_16 (0x1U << 1)

Destination Transfer Width is 16 bits

## ◆ DMAC_CTLL_DST_TR_WIDTH_32

#define DMAC_CTLL_DST_TR_WIDTH_32 (0x2U << 1)

Destination Transfer Width is 32 bits

## ◆ DMAC_CTLL_DST_TR_WIDTH_8

#define DMAC_CTLL_DST_TR_WIDTH_8 (0x0U << 1)

Destination Transfer Width is 8 bits

## ◆ DMAC_CTLL_DST_TR_WIDTH_Msk

#define DMAC_CTLL_DST_TR_WIDTH_Msk (0x7U << 1)

Destination Transfer Width field mask bit

## ◆ DMAC_CTLL_INT_EN

#define DMAC_CTLL_INT_EN (0x1U << 0)

Interrupt Enable Bit

## ◆ DMAC_CTLL_LLP_DST_EN

#define DMAC_CTLL_LLP_DST_EN (0x1U << 27)

Source Burst Transaction Length

## ◆ DMAC_CTLL_LLP_SRC_EN

#define DMAC_CTLL_LLP_SRC_EN (0x1U << 28)

Block chaining is enabled on the source side

## ◆ DMAC_CTLL_SINC_DEC

#define DMAC_CTLL_SINC_DEC (0x1U << 9)

Source Address Increment is decrement

## ◆ DMAC_CTLL_SINC_INC

#define DMAC_CTLL_SINC_INC (0x0U << 9)

Source Address Increment is increment

## ◆ DMAC_CTLL_SINC_Msk

#define DMAC_CTLL_SINC_Msk (0x3U << 9)

Source Address Increment field mask bit

## ◆ DMAC_CTLL_SINC_NO

#define DMAC_CTLL_SINC_NO (0x2U << 9)

Source Address Increment is no change

## ◆ DMAC_CTLL_SRC_GATHER_EN

#define DMAC_CTLL_SRC_GATHER_EN (0x1U << 17)

Source gather enable bit

## ◆ DMAC_CTLL_SRC_MSIZE_1

#define DMAC_CTLL_SRC_MSIZE_1 (0x0U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_128

#define DMAC_CTLL_SRC_MSIZE_128 (0x6U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_16

#define DMAC_CTLL_SRC_MSIZE_16 (0x3U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_256

#define DMAC_CTLL_SRC_MSIZE_256 (0x7U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_32

#define DMAC_CTLL_SRC_MSIZE_32 (0x4U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_4

#define DMAC_CTLL_SRC_MSIZE_4 (0x1U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_64

#define DMAC_CTLL_SRC_MSIZE_64 (0x5U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_8

#define DMAC_CTLL_SRC_MSIZE_8 (0x2U << 14)

Source Burst Transaction Length

## ◆ DMAC_CTLL_SRC_MSIZE_Msk

#define DMAC_CTLL_SRC_MSIZE_Msk (0x7U << 14)

Source Burst Transaction Length field mask bit

## ◆ DMAC_CTLL_SRC_TR_WIDTH_16

#define DMAC_CTLL_SRC_TR_WIDTH_16 (0x1U << 4)

Source Transfer Width is 16 bits

## ◆ DMAC_CTLL_SRC_TR_WIDTH_32

#define DMAC_CTLL_SRC_TR_WIDTH_32 (0x2U << 4)

Source Transfer Width is 32 bits

## ◆ DMAC_CTLL_SRC_TR_WIDTH_8

#define DMAC_CTLL_SRC_TR_WIDTH_8 (0x0U << 4)

Source Transfer Width is 8 bits

## ◆ DMAC_CTLL_SRC_TR_WIDTH_Msk

#define DMAC_CTLL_SRC_TR_WIDTH_Msk (0x7U << 4)

Source Transfer Width field mask bit

## ◆ DMAC_CTLL_TT_FC_M2M_DMAC

#define DMAC_CTLL_TT_FC_M2M_DMAC (0x0U << 20)

Transfer Type is Memory to Memory, Flow Control is DMAC

## ◆ DMAC_CTLL_TT_FC_M2P_DMAC

#define DMAC_CTLL_TT_FC_M2P_DMAC (0x1U << 20)

Transfer Type is Memory to Peripheral, Flow Control is DMAC

## ◆ DMAC_CTLL_TT_FC_M2P_PERIPH

#define DMAC_CTLL_TT_FC_M2P_PERIPH (0x6U << 20)

Transfer Type is Memory to Peripheral, Flow Control is Peripheral

## ◆ DMAC_CTLL_TT_FC_Msk

#define DMAC_CTLL_TT_FC_Msk (0x7U << 20)

Transfer Type and Flow Control field mask bit

## ◆ DMAC_CTLL_TT_FC_P2M_DMAC

#define DMAC_CTLL_TT_FC_P2M_DMAC (0x2U << 20)

Transfer Type is Peripheral to Memory, Flow Control is DMAC

## ◆ DMAC_CTLL_TT_FC_P2M_PERIPH

#define DMAC_CTLL_TT_FC_P2M_PERIPH (0x4U << 20)

Transfer Type is Peripheral to Memory, Flow Control is Peripheral

## ◆ DMAC_CTLL_TT_FC_P2P_DMAC

#define DMAC_CTLL_TT_FC_P2P_DMAC (0x3U << 20)

Transfer Type is Peripheral to Peripheral, Flow Control is DMAC

## ◆ DMAC_CTLL_TT_FC_P2P_DST_PERIPH

#define DMAC_CTLL_TT_FC_P2P_DST_PERIPH (0x7U << 20)

Transfer Type is Peripheral to Peripheral, Flow Control is Destination Peripheral

## ◆ DMAC_CTLL_TT_FC_P2P_SRC_PERIPH

#define DMAC_CTLL_TT_FC_P2P_SRC_PERIPH (0x5U << 20)

Transfer Type is Peripheral to Peripheral, Flow Control is Source Peripheral

## ◆ EXTI_EMR_MR0

#define EXTI_EMR_MR0 ((uint32_t)0x00000001)

Event Mask on line 0

## ◆ EXTI_EMR_MR1

#define EXTI_EMR_MR1 ((uint32_t)0x00000002)

Event Mask on line 1

## ◆ EXTI_EMR_MR10

#define EXTI_EMR_MR10 ((uint32_t)0x00000400)

Event Mask on line 10

## ◆ EXTI_EMR_MR11

#define EXTI_EMR_MR11 ((uint32_t)0x00000800)

Event Mask on line 11

## ◆ EXTI_EMR_MR12

#define EXTI_EMR_MR12 ((uint32_t)0x00001000)

Event Mask on line 12

## ◆ EXTI_EMR_MR13

#define EXTI_EMR_MR13 ((uint32_t)0x00002000)

Event Mask on line 13

## ◆ EXTI_EMR_MR14

#define EXTI_EMR_MR14 ((uint32_t)0x00004000)

Event Mask on line 14

## ◆ EXTI_EMR_MR15

#define EXTI_EMR_MR15 ((uint32_t)0x00008000)

Event Mask on line 15

## ◆ EXTI_EMR_MR16

#define EXTI_EMR_MR16 ((uint32_t)0x00010000)

Event Mask on line 16

## ◆ EXTI_EMR_MR17

#define EXTI_EMR_MR17 ((uint32_t)0x00020000)

Event Mask on line 17

## ◆ EXTI_EMR_MR18

#define EXTI_EMR_MR18 ((uint32_t)0x00040000)

Event Mask on line 18

## ◆ EXTI_EMR_MR2

#define EXTI_EMR_MR2 ((uint32_t)0x00000004)

Event Mask on line 2

## ◆ EXTI_EMR_MR3

#define EXTI_EMR_MR3 ((uint32_t)0x00000008)

Event Mask on line 3

## ◆ EXTI_EMR_MR4

#define EXTI_EMR_MR4 ((uint32_t)0x00000010)

Event Mask on line 4

## ◆ EXTI_EMR_MR5

#define EXTI_EMR_MR5 ((uint32_t)0x00000020)

Event Mask on line 5

## ◆ EXTI_EMR_MR6

#define EXTI_EMR_MR6 ((uint32_t)0x00000040)

Event Mask on line 6

## ◆ EXTI_EMR_MR7

#define EXTI_EMR_MR7 ((uint32_t)0x00000080)

Event Mask on line 7

## ◆ EXTI_EMR_MR8

#define EXTI_EMR_MR8 ((uint32_t)0x00000100)

Event Mask on line 8

## ◆ EXTI_EMR_MR9

#define EXTI_EMR_MR9 ((uint32_t)0x00000200)

Event Mask on line 9

## ◆ EXTI_FTSR_TR0

#define EXTI_FTSR_TR0 ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

## ◆ EXTI_FTSR_TR1

#define EXTI_FTSR_TR1 ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

## ◆ EXTI_FTSR_TR10

#define EXTI_FTSR_TR10 ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

## ◆ EXTI_FTSR_TR11

#define EXTI_FTSR_TR11 ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

## ◆ EXTI_FTSR_TR12

#define EXTI_FTSR_TR12 ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

## ◆ EXTI_FTSR_TR13

#define EXTI_FTSR_TR13 ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

## ◆ EXTI_FTSR_TR14

#define EXTI_FTSR_TR14 ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

## ◆ EXTI_FTSR_TR15

#define EXTI_FTSR_TR15 ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

## ◆ EXTI_FTSR_TR16

#define EXTI_FTSR_TR16 ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

## ◆ EXTI_FTSR_TR17

#define EXTI_FTSR_TR17 ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

## ◆ EXTI_FTSR_TR18

#define EXTI_FTSR_TR18 ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

## ◆ EXTI_FTSR_TR2

#define EXTI_FTSR_TR2 ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

## ◆ EXTI_FTSR_TR3

#define EXTI_FTSR_TR3 ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

## ◆ EXTI_FTSR_TR4

#define EXTI_FTSR_TR4 ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

## ◆ EXTI_FTSR_TR5

#define EXTI_FTSR_TR5 ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

## ◆ EXTI_FTSR_TR6

#define EXTI_FTSR_TR6 ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

## ◆ EXTI_FTSR_TR7

#define EXTI_FTSR_TR7 ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

## ◆ EXTI_FTSR_TR8

#define EXTI_FTSR_TR8 ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

## ◆ EXTI_FTSR_TR9

#define EXTI_FTSR_TR9 ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

## ◆ EXTI_IMR_MR0

#define EXTI_IMR_MR0 ((uint32_t)0x00000001)

Interrupt Mask on line 0

## ◆ EXTI_IMR_MR1

#define EXTI_IMR_MR1 ((uint32_t)0x00000002)

Interrupt Mask on line 1

## ◆ EXTI_IMR_MR10

#define EXTI_IMR_MR10 ((uint32_t)0x00000400)

Interrupt Mask on line 10

## ◆ EXTI_IMR_MR11

#define EXTI_IMR_MR11 ((uint32_t)0x00000800)

Interrupt Mask on line 11

## ◆ EXTI_IMR_MR12

#define EXTI_IMR_MR12 ((uint32_t)0x00001000)

Interrupt Mask on line 12

## ◆ EXTI_IMR_MR13

#define EXTI_IMR_MR13 ((uint32_t)0x00002000)

Interrupt Mask on line 13

## ◆ EXTI_IMR_MR14

#define EXTI_IMR_MR14 ((uint32_t)0x00004000)

Interrupt Mask on line 14

## ◆ EXTI_IMR_MR15

#define EXTI_IMR_MR15 ((uint32_t)0x00008000)

Interrupt Mask on line 15

## ◆ EXTI_IMR_MR16

#define EXTI_IMR_MR16 ((uint32_t)0x00010000)

Interrupt Mask on line 16

## ◆ EXTI_IMR_MR17

#define EXTI_IMR_MR17 ((uint32_t)0x00020000)

Interrupt Mask on line 17

## ◆ EXTI_IMR_MR18

#define EXTI_IMR_MR18 ((uint32_t)0x00040000)

Interrupt Mask on line 18

## ◆ EXTI_IMR_MR2

#define EXTI_IMR_MR2 ((uint32_t)0x00000004)

Interrupt Mask on line 2

## ◆ EXTI_IMR_MR3

#define EXTI_IMR_MR3 ((uint32_t)0x00000008)

Interrupt Mask on line 3

## ◆ EXTI_IMR_MR4

#define EXTI_IMR_MR4 ((uint32_t)0x00000010)

Interrupt Mask on line 4

## ◆ EXTI_IMR_MR5

#define EXTI_IMR_MR5 ((uint32_t)0x00000020)

Interrupt Mask on line 5

## ◆ EXTI_IMR_MR6

#define EXTI_IMR_MR6 ((uint32_t)0x00000040)

Interrupt Mask on line 6

## ◆ EXTI_IMR_MR7

#define EXTI_IMR_MR7 ((uint32_t)0x00000080)

Interrupt Mask on line 7

## ◆ EXTI_IMR_MR8

#define EXTI_IMR_MR8 ((uint32_t)0x00000100)

Interrupt Mask on line 8

## ◆ EXTI_IMR_MR9

#define EXTI_IMR_MR9 ((uint32_t)0x00000200)

Interrupt Mask on line 9

## ◆ EXTI_PR_PR0

#define EXTI_PR_PR0 ((uint32_t)0x00000001)

Pending bit for line 0

## ◆ EXTI_PR_PR1

#define EXTI_PR_PR1 ((uint32_t)0x00000002)

Pending bit for line 1

## ◆ EXTI_PR_PR10

#define EXTI_PR_PR10 ((uint32_t)0x00000400)

Pending bit for line 10

## ◆ EXTI_PR_PR11

#define EXTI_PR_PR11 ((uint32_t)0x00000800)

Pending bit for line 11

## ◆ EXTI_PR_PR12

#define EXTI_PR_PR12 ((uint32_t)0x00001000)

Pending bit for line 12

## ◆ EXTI_PR_PR13

#define EXTI_PR_PR13 ((uint32_t)0x00002000)

Pending bit for line 13

## ◆ EXTI_PR_PR14

#define EXTI_PR_PR14 ((uint32_t)0x00004000)

Pending bit for line 14

## ◆ EXTI_PR_PR15

#define EXTI_PR_PR15 ((uint32_t)0x00008000)

Pending bit for line 15

## ◆ EXTI_PR_PR16

#define EXTI_PR_PR16 ((uint32_t)0x00010000)

Pending bit for line 16

## ◆ EXTI_PR_PR17

#define EXTI_PR_PR17 ((uint32_t)0x00020000)

Pending bit for line 17

## ◆ EXTI_PR_PR18

#define EXTI_PR_PR18 ((uint32_t)0x00040000)

Pending bit for line 18

## ◆ EXTI_PR_PR2

#define EXTI_PR_PR2 ((uint32_t)0x00000004)

Pending bit for line 2

## ◆ EXTI_PR_PR3

#define EXTI_PR_PR3 ((uint32_t)0x00000008)

Pending bit for line 3

## ◆ EXTI_PR_PR4

#define EXTI_PR_PR4 ((uint32_t)0x00000010)

Pending bit for line 4

## ◆ EXTI_PR_PR5

#define EXTI_PR_PR5 ((uint32_t)0x00000020)

Pending bit for line 5

## ◆ EXTI_PR_PR6

#define EXTI_PR_PR6 ((uint32_t)0x00000040)

Pending bit for line 6

## ◆ EXTI_PR_PR7

#define EXTI_PR_PR7 ((uint32_t)0x00000080)

Pending bit for line 7

## ◆ EXTI_PR_PR8

#define EXTI_PR_PR8 ((uint32_t)0x00000100)

Pending bit for line 8

## ◆ EXTI_PR_PR9

#define EXTI_PR_PR9 ((uint32_t)0x00000200)

Pending bit for line 9

## ◆ EXTI_RTSR_TR0

#define EXTI_RTSR_TR0 ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

## ◆ EXTI_RTSR_TR1

#define EXTI_RTSR_TR1 ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

## ◆ EXTI_RTSR_TR10

#define EXTI_RTSR_TR10 ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

## ◆ EXTI_RTSR_TR11

#define EXTI_RTSR_TR11 ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

## ◆ EXTI_RTSR_TR12

#define EXTI_RTSR_TR12 ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

## ◆ EXTI_RTSR_TR13

#define EXTI_RTSR_TR13 ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

## ◆ EXTI_RTSR_TR14

#define EXTI_RTSR_TR14 ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

## ◆ EXTI_RTSR_TR15

#define EXTI_RTSR_TR15 ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

## ◆ EXTI_RTSR_TR16

#define EXTI_RTSR_TR16 ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

## ◆ EXTI_RTSR_TR17

#define EXTI_RTSR_TR17 ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

## ◆ EXTI_RTSR_TR18

#define EXTI_RTSR_TR18 ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

## ◆ EXTI_RTSR_TR2

#define EXTI_RTSR_TR2 ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

## ◆ EXTI_RTSR_TR3

#define EXTI_RTSR_TR3 ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

## ◆ EXTI_RTSR_TR4

#define EXTI_RTSR_TR4 ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

## ◆ EXTI_RTSR_TR5

#define EXTI_RTSR_TR5 ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

## ◆ EXTI_RTSR_TR6

#define EXTI_RTSR_TR6 ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

## ◆ EXTI_RTSR_TR7

#define EXTI_RTSR_TR7 ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

## ◆ EXTI_RTSR_TR8

#define EXTI_RTSR_TR8 ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

## ◆ EXTI_RTSR_TR9

#define EXTI_RTSR_TR9 ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

## ◆ EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)

Software Interrupt on line 0

## ◆ EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)

Software Interrupt on line 1

## ◆ EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)

Software Interrupt on line 10

## ◆ EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)

Software Interrupt on line 11

## ◆ EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)

Software Interrupt on line 12

## ◆ EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)

Software Interrupt on line 13

## ◆ EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)

Software Interrupt on line 14

## ◆ EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)

Software Interrupt on line 15

## ◆ EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)

Software Interrupt on line 16

## ◆ EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)

Software Interrupt on line 17

## ◆ EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)

Software Interrupt on line 18

## ◆ EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)

Software Interrupt on line 2

## ◆ EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)

Software Interrupt on line 3

## ◆ EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)

Software Interrupt on line 4

## ◆ EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)

Software Interrupt on line 5

## ◆ EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)

Software Interrupt on line 6

## ◆ EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)

Software Interrupt on line 7

## ◆ EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)

Software Interrupt on line 8

## ◆ EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)

Software Interrupt on line 9

## ◆ FHSI_VALUE

#define FHSI_VALUE (48000000)

Value of the Internal 48M oscillator in Hz

## ◆ FLASH_BASE

#define FLASH_BASE ((uint32_t)0x08000000UL)

FLASH base address in the alias region

## ◆ FMC_CON_OP_Msk

#define FMC_CON_OP_Msk (0x1FU)

OP field mask bit

## ◆ FMC_CON_SETHLDCNT_Msk

#define FMC_CON_SETHLDCNT_Msk (0x7FU << 8)

SETHLDCNT field mask bit

## ◆ GPIO_BSRR_BR0

#define GPIO_BSRR_BR0 (0x1U << 16)

Port x Reset bit 0

## ◆ GPIO_BSRR_BR1

#define GPIO_BSRR_BR1 (0x1U << 17)

Port x Reset bit 1

## ◆ GPIO_BSRR_BR10

#define GPIO_BSRR_BR10 (0x1U << 26)

Port x Reset bit 10

## ◆ GPIO_BSRR_BR11

#define GPIO_BSRR_BR11 (0x1U << 27)

Port x Reset bit 11

## ◆ GPIO_BSRR_BR12

#define GPIO_BSRR_BR12 (0x1U << 28)

Port x Reset bit 12

## ◆ GPIO_BSRR_BR13

#define GPIO_BSRR_BR13 (0x1U << 29)

Port x Reset bit 13

## ◆ GPIO_BSRR_BR14

#define GPIO_BSRR_BR14 (0x1U << 30)

Port x Reset bit 14

## ◆ GPIO_BSRR_BR15

#define GPIO_BSRR_BR15 (0x1U << 31)

Port x Reset bit 15

## ◆ GPIO_BSRR_BR2

#define GPIO_BSRR_BR2 (0x1U << 18)

Port x Reset bit 2

## ◆ GPIO_BSRR_BR3

#define GPIO_BSRR_BR3 (0x1U << 19)

Port x Reset bit 3

## ◆ GPIO_BSRR_BR4

#define GPIO_BSRR_BR4 (0x1U << 20)

Port x Reset bit 4

## ◆ GPIO_BSRR_BR5

#define GPIO_BSRR_BR5 (0x1U << 21)

Port x Reset bit 5

## ◆ GPIO_BSRR_BR6

#define GPIO_BSRR_BR6 (0x1U << 22)

Port x Reset bit 6

## ◆ GPIO_BSRR_BR7

#define GPIO_BSRR_BR7 (0x1U << 23)

Port x Reset bit 7

## ◆ GPIO_BSRR_BR8

#define GPIO_BSRR_BR8 (0x1U << 24)

Port x Reset bit 8

## ◆ GPIO_BSRR_BR9

#define GPIO_BSRR_BR9 (0x1U << 25)

Port x Reset bit 9

## ◆ GPIO_BSRR_BS0

#define GPIO_BSRR_BS0 (0x1U << 0)

Port x Set bit 0

## ◆ GPIO_BSRR_BS1

#define GPIO_BSRR_BS1 (0x1U << 1)

Port x Set bit 1

## ◆ GPIO_BSRR_BS10

#define GPIO_BSRR_BS10 (0x1U << 10)

Port x Set bit 10

## ◆ GPIO_BSRR_BS11

#define GPIO_BSRR_BS11 (0x1U << 11)

Port x Set bit 11

## ◆ GPIO_BSRR_BS12

#define GPIO_BSRR_BS12 (0x1U << 12)

Port x Set bit 12

## ◆ GPIO_BSRR_BS13

#define GPIO_BSRR_BS13 (0x1U << 13)

Port x Set bit 13

## ◆ GPIO_BSRR_BS14

#define GPIO_BSRR_BS14 (0x1U << 14)

Port x Set bit 14

## ◆ GPIO_BSRR_BS15

#define GPIO_BSRR_BS15 (0x1U << 15)

Port x Set bit 15

## ◆ GPIO_BSRR_BS2

#define GPIO_BSRR_BS2 (0x1U << 2)

Port x Set bit 2

## ◆ GPIO_BSRR_BS3

#define GPIO_BSRR_BS3 (0x1U << 3)

Port x Set bit 3

## ◆ GPIO_BSRR_BS4

#define GPIO_BSRR_BS4 (0x1U << 4)

Port x Set bit 4

## ◆ GPIO_BSRR_BS5

#define GPIO_BSRR_BS5 (0x1U << 5)

Port x Set bit 5

## ◆ GPIO_BSRR_BS6

#define GPIO_BSRR_BS6 (0x1U << 6)

Port x Set bit 6

## ◆ GPIO_BSRR_BS7

#define GPIO_BSRR_BS7 (0x1U << 7)

Port x Set bit 7

## ◆ GPIO_BSRR_BS8

#define GPIO_BSRR_BS8 (0x1U << 8)

Port x Set bit 8

## ◆ GPIO_BSRR_BS9

#define GPIO_BSRR_BS9 (0x1U << 9)

Port x Set bit 9

## ◆ GPIO_IDR_IDR0

#define GPIO_IDR_IDR0 (0x1U << 0)

Port input data, bit 0

## ◆ GPIO_IDR_IDR1

#define GPIO_IDR_IDR1 (0x1U << 1)

Port input data, bit 1

## ◆ GPIO_IDR_IDR10

#define GPIO_IDR_IDR10 (0x1U << 10)

Port input data, bit 10

## ◆ GPIO_IDR_IDR11

#define GPIO_IDR_IDR11 (0x1U << 11)

Port input data, bit 11

## ◆ GPIO_IDR_IDR12

#define GPIO_IDR_IDR12 (0x1U << 12)

Port input data, bit 12

## ◆ GPIO_IDR_IDR13

#define GPIO_IDR_IDR13 (0x1U << 13)

Port input data, bit 13

## ◆ GPIO_IDR_IDR14

#define GPIO_IDR_IDR14 (0x1U << 14)

Port input data, bit 14

## ◆ GPIO_IDR_IDR15

#define GPIO_IDR_IDR15 (0x1U << 15)

Port input data, bit 15

## ◆ GPIO_IDR_IDR2

#define GPIO_IDR_IDR2 (0x1U << 2)

Port input data, bit 2

## ◆ GPIO_IDR_IDR3

#define GPIO_IDR_IDR3 (0x1U << 3)

Port input data, bit 3

## ◆ GPIO_IDR_IDR4

#define GPIO_IDR_IDR4 (0x1U << 4)

Port input data, bit 4

## ◆ GPIO_IDR_IDR5

#define GPIO_IDR_IDR5 (0x1U << 5)

Port input data, bit 5

## ◆ GPIO_IDR_IDR6

#define GPIO_IDR_IDR6 (0x1U << 6)

Port input data, bit 6

## ◆ GPIO_IDR_IDR7

#define GPIO_IDR_IDR7 (0x1U << 7)

Port input data, bit 7

## ◆ GPIO_IDR_IDR8

#define GPIO_IDR_IDR8 (0x1U << 8)

Port input data, bit 8

## ◆ GPIO_IDR_IDR9

#define GPIO_IDR_IDR9 (0x1U << 9)

Port input data, bit 9

## ◆ GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK0 (0x1U << 0)

Port x Lock bit 0

## ◆ GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK1 (0x1U << 1)

Port x Lock bit 1

## ◆ GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK10 (0x1U << 10)

Port x Lock bit 10

## ◆ GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK11 (0x1U << 11)

Port x Lock bit 11

## ◆ GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK12 (0x1U << 12)

Port x Lock bit 12

## ◆ GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK13 (0x1U << 13)

Port x Lock bit 13

## ◆ GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK14 (0x1U << 14)

Port x Lock bit 14

## ◆ GPIO_LCKR_LCK15

#define GPIO_LCKR_LCK15 (0x1U << 15)

Port x Lock bit 15

## ◆ GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK2 (0x1U << 2)

Port x Lock bit 2

## ◆ GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK3 (0x1U << 3)

Port x Lock bit 3

## ◆ GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK4 (0x1U << 4)

Port x Lock bit 4

## ◆ GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK5 (0x1U << 5)

Port x Lock bit 5

## ◆ GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK6 (0x1U << 6)

Port x Lock bit 6

## ◆ GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK7 (0x1U << 7)

Port x Lock bit 7

## ◆ GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK8 (0x1U << 8)

Port x Lock bit 8

## ◆ GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK9 (0x1U << 9)

Port x Lock bit 9

## ◆ GPIO_LCKR_LCKK

#define GPIO_LCKR_LCKK (0x1U << 16)

Lock key

## ◆ GPIO_ODR_ODR0

#define GPIO_ODR_ODR0 (0x1U << 0)

Port output data, bit 0

## ◆ GPIO_ODR_ODR1

#define GPIO_ODR_ODR1 (0x1U << 1)

Port output data, bit 1

## ◆ GPIO_ODR_ODR10

#define GPIO_ODR_ODR10 (0x1U << 10)

Port output data, bit 10

## ◆ GPIO_ODR_ODR11

#define GPIO_ODR_ODR11 (0x1U << 11)

Port output data, bit 11

## ◆ GPIO_ODR_ODR12

#define GPIO_ODR_ODR12 (0x1U << 12)

Port output data, bit 12

## ◆ GPIO_ODR_ODR13

#define GPIO_ODR_ODR13 (0x1U << 13)

Port output data, bit 13

## ◆ GPIO_ODR_ODR14

#define GPIO_ODR_ODR14 (0x1U << 14)

Port output data, bit 14

## ◆ GPIO_ODR_ODR15

#define GPIO_ODR_ODR15 (0x1U << 15)

Port output data, bit 15

## ◆ GPIO_ODR_ODR2

#define GPIO_ODR_ODR2 (0x1U << 2)

Port output data, bit 2

## ◆ GPIO_ODR_ODR3

#define GPIO_ODR_ODR3 (0x1U << 3)

Port output data, bit 3

## ◆ GPIO_ODR_ODR4

#define GPIO_ODR_ODR4 (0x1U << 4)

Port output data, bit 4

## ◆ GPIO_ODR_ODR5

#define GPIO_ODR_ODR5 (0x1U << 5)

Port output data, bit 5

## ◆ GPIO_ODR_ODR6

#define GPIO_ODR_ODR6 (0x1U << 6)

Port output data, bit 6

## ◆ GPIO_ODR_ODR7

#define GPIO_ODR_ODR7 (0x1U << 7)

Port output data, bit 7

## ◆ GPIO_ODR_ODR8

#define GPIO_ODR_ODR8 (0x1U << 8)

Port output data, bit 8

## ◆ GPIO_ODR_ODR9

#define GPIO_ODR_ODR9 (0x1U << 9)

Port output data, bit 9

## ◆ I2C_CON_10BITADDR_MASTER

#define I2C_CON_10BITADDR_MASTER (0x1U << 4)

XXX

## ◆ I2C_CON_10BITADDR_SLAVE

#define I2C_CON_10BITADDR_SLAVE (0x1U << 3)

When acting as a slave, this bit controls i2c responds to 10-bit addresses.

## ◆ I2C_CON_BUS_CLEAR_FEATURE_CTRL

#define I2C_CON_BUS_CLEAR_FEATURE_CTRL (0x1U << 11)

XXX

## ◆ I2C_CON_MASTER_MODE

#define I2C_CON_MASTER_MODE (0x1U << 0)

This bit controls whether the i2c master is enable

## ◆ I2C_CON_OPTIONAL_SAR_CTRL

#define I2C_CON_OPTIONAL_SAR_CTRL (0x1U << 16)

Enables the usage of OPTIONAL_SAR register

## ◆ I2C_CON_RESTART_EN

#define I2C_CON_RESTART_EN (0x1U << 5)

Determines whether RESTART conditions may be sent when acting as a master.

## ◆ I2C_CON_RX_FIFO_FULL_HLD_CTRL

#define I2C_CON_RX_FIFO_FULL_HLD_CTRL (0x1U << 9)

This bit controls whether i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH

## ◆ I2C_CON_SLAVE_DISABLE

#define I2C_CON_SLAVE_DISABLE (0x1U << 6)

This bit controls whether I2C has its slave disabled

## ◆ I2C_CON_SMBUS_ARP_EN

#define I2C_CON_SMBUS_ARP_EN (0x1U << 18)

This bit controls whether i2c should enable Address Resolution Logic in SMBus Mode

## ◆ I2C_CON_SMBUS_PERSISTANT_SLV_ADDR_EN

#define I2C_CON_SMBUS_PERSISTANT_SLV_ADDR_EN (0x1U << 19)

This bit controls to enable i2c slave as persistent or non-persistent slave

## ◆ I2C_CON_SMBUS_SLAVE_QUICK_EN

#define I2C_CON_SMBUS_SLAVE_QUICK_EN (0x1U << 17)

XXX

## ◆ I2C_CON_SPEED_FAST

#define I2C_CON_SPEED_FAST (0x2U << 1)

fast mode (≤ 400 Kb/s) or fast mode plus (≤ 1000 Kb/s)

## ◆ I2C_CON_SPEED_HIGH

#define I2C_CON_SPEED_HIGH (0x3U << 1)

high speed mode (≤ 3.4 Mb/s)

## ◆ I2C_CON_SPEED_Msk

#define I2C_CON_SPEED_Msk (0x3U << 1)

SPEED field mask bit

## ◆ I2C_CON_SPEED_STANDARD

#define I2C_CON_SPEED_STANDARD (0x1U << 1)

standard mode (0 to 100 Kb/s)

## ◆ I2C_CON_STOP_DET_IF_MASTER_ACTIVE

#define I2C_CON_STOP_DET_IF_MASTER_ACTIVE (0x1U << 10)

XXX

## ◆ I2C_CON_STOP_DET_IFADDRESSED

#define I2C_CON_STOP_DET_IFADDRESSED (0x1U << 7)

XXX

## ◆ I2C_CON_TX_EMPTY_CTRL

#define I2C_CON_TX_EMPTY_CTRL (0x1U << 8)

This bit controls the generation of the TX_EMPTY interrupt

## ◆ I2C_DATA_CMD_DAT_Msk

#define I2C_DATA_CMD_DAT_Msk (0xFFU)

DAT field mask bit

## ◆ I2C_DATA_CMD_FIRST_DATA_BYTE

#define I2C_DATA_CMD_FIRST_DATA_BYTE (0x1U << 11)

Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode

## ◆ I2C_DATA_CMD_READ

#define I2C_DATA_CMD_READ (0x1U << 8)

This bit controls whether a read or a write is performed

## ◆ I2C_DATA_CMD_RESTART

#define I2C_DATA_CMD_RESTART (0x1U << 10)

This bit controls whether a RESTART is issued before the byte is sent or received

## ◆ I2C_DATA_CMD_STOP

#define I2C_DATA_CMD_STOP (0x1U << 9)

This bit controls whether a STOP is issued after the byte is sent or received

## ◆ I2C_DMA_CR_RDMAE

#define I2C_DMA_CR_RDMAE (0x1U << 0)

XXX

## ◆ I2C_DMA_CR_TDMAE

#define I2C_DMA_CR_TDMAE (0x1U << 1)

XXX

## ◆ I2C_ENABLE_ABORT

#define I2C_ENABLE_ABORT (0x1U << 1)

XXX

## ◆ I2C_ENABLE_ENABLE

#define I2C_ENABLE_ENABLE (0x1U << 0)

Controls whether the DW_apb_i2c is enabled

## ◆ I2C_ENABLE_SDA_STUCK_RECOVERY_ENA

#define I2C_ENABLE_SDA_STUCK_RECOVERY_ENA (0x1U << 3)

XXX

## ◆ I2C_ENABLE_SMBUS_ALERT_EN

#define I2C_ENABLE_SMBUS_ALERT_EN (0x1U << 18)

The SMBUS_ALERT_CTRL register bit is used to control assertion of SMBALERT signal

## ◆ I2C_ENABLE_SMBUS_CLK_RESET

#define I2C_ENABLE_SMBUS_CLK_RESET (0x1U << 16)

This bit is used in SMBus Host mode to initiate the SMBus Master Clock Reset

## ◆ I2C_ENABLE_SMBUS_SUSPEND_EN

#define I2C_ENABLE_SMBUS_SUSPEND_EN (0x1U << 17)

The SMBUS_SUSPEND_EN register bit is used to control assertion and de-assertion of SMBSUS signal

## ◆ I2C_ENABLE_STATUS_IC_EN

#define I2C_ENABLE_STATUS_IC_EN (0x1U << 0)

XXX

## ◆ I2C_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY

#define I2C_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY (0x1U << 1)

XXX

## ◆ I2C_ENABLE_STATUS_SLV_RX_DATA_LOST

#define I2C_ENABLE_STATUS_SLV_RX_DATA_LOST (0x1U << 2)

XXX

## ◆ I2C_ENABLE_TX_CMD_BLOCK

#define I2C_ENABLE_TX_CMD_BLOCK (0x1U << 2)

XXX

## ◆ I2C_INTR_ACTIVITY

#define I2C_INTR_ACTIVITY (0x1U << 8)

This bit captures DW_apb_i2c activity and stays set until it is cleared

## ◆ I2C_INTR_GEN_CALL

#define I2C_INTR_GEN_CALL (0x1U << 11)

Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode

## ◆ I2C_INTR_RD_REQ

#define I2C_INTR_RD_REQ (0x1U << 5)

This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c

## ◆ I2C_INTR_RESTART_DET

#define I2C_INTR_RESTART_DET (0x1U << 12)

Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave

## ◆ I2C_INTR_RX_DONE

#define I2C_INTR_RX_DONE (0x1U << 7)

When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte

## ◆ I2C_INTR_RX_FULL

#define I2C_INTR_RX_FULL (0x1U << 2)

Set when the receive buffer reaches or goes above the RX_TL threshold in the RX_TL register

## ◆ I2C_INTR_RX_OVER

#define I2C_INTR_RX_OVER (0x1U << 1)

Set if the receive buffer is completely filled to RX_BUFFER_DEPTH and an additional byte is received from an external I2C device

## ◆ I2C_INTR_RX_UNDER

#define I2C_INTR_RX_UNDER (0x1U << 0)

Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register

## ◆ I2C_INTR_SCL_STUCK_AT_LOW

#define I2C_INTR_SCL_STUCK_AT_LOW (0x1U << 14)

Indicates whether the SCL Line is stuck at low for the SCL_STUCK_LOW_TIMOUT number of clk periods

## ◆ I2C_INTR_START_DET

#define I2C_INTR_START_DET (0x1U << 10)

Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode

## ◆ I2C_INTR_STOP_DET

#define I2C_INTR_STOP_DET (0x1U << 9)

Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode

## ◆ I2C_INTR_TX_ABRT

#define I2C_INTR_TX_ABRT (0x1U << 6)

This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO

## ◆ I2C_INTR_TX_EMPTY

#define I2C_INTR_TX_EMPTY (0x1U << 4)

The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the CON register

## ◆ I2C_INTR_TX_OVER

#define I2C_INTR_TX_OVER (0x1U << 3)

Set during transmit if the transmit buffer is filled to TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the DATA_CMD register

## ◆ I2C_SLV_DATA_NACK_ONLY_NACK

#define I2C_SLV_DATA_NACK_ONLY_NACK (0x1U << 0)

XXX

## ◆ I2C_SMBUS_INTR_ARP_ASSGN_ADDR_CMD_DET

#define I2C_SMBUS_INTR_ARP_ASSGN_ADDR_CMD_DET (0x1U << 7)

XXX

## ◆ I2C_SMBUS_INTR_ARP_GET_UDID_CMD_DET

#define I2C_SMBUS_INTR_ARP_GET_UDID_CMD_DET (0x1U << 6)

XXX

## ◆ I2C_SMBUS_INTR_ARP_PREPARE_CMD_DET

#define I2C_SMBUS_INTR_ARP_PREPARE_CMD_DET (0x1U << 4)

XXX

## ◆ I2C_SMBUS_INTR_ARP_RST_CMD_DET

#define I2C_SMBUS_INTR_ARP_RST_CMD_DET (0x1U << 5)

XXX

## ◆ I2C_SMBUS_INTR_HOST_NTFY_MST_DET

#define I2C_SMBUS_INTR_HOST_NTFY_MST_DET (0x1U << 3)

XXX

## ◆ I2C_SMBUS_INTR_MST_CLOCK_EXTND_TIMEOUT

#define I2C_SMBUS_INTR_MST_CLOCK_EXTND_TIMEOUT (0x1U << 1)

XXX

## ◆ I2C_SMBUS_INTR_QUICK_CMD_DET

#define I2C_SMBUS_INTR_QUICK_CMD_DET (0x1U << 2)

XXX

## ◆ I2C_SMBUS_INTR_SLV_CLOCK_EXTND_TIMEOUT

#define I2C_SMBUS_INTR_SLV_CLOCK_EXTND_TIMEOUT (0x1U << 0)

XXX

## ◆ I2C_SMBUS_INTR_SLV_RX_PEC_NACK

#define I2C_SMBUS_INTR_SLV_RX_PEC_NACK (0x1U << 8)

XXX

## ◆ I2C_SMBUS_INTR_SMBUS_ALERT_DET

#define I2C_SMBUS_INTR_SMBUS_ALERT_DET (0x1U << 10)

XXX

## ◆ I2C_SMBUS_INTR_SMBUS_SUSPEND_DET

#define I2C_SMBUS_INTR_SMBUS_SUSPEND_DET (0x1U << 9)

XXX

## ◆ I2C_STATUS_ACTIVITY

#define I2C_STATUS_ACTIVITY (0x1U << 0)

I2C Activity Status

## ◆ I2C_STATUS_MST_ACTIVITY

#define I2C_STATUS_MST_ACTIVITY (0x1U << 5)

Master FSM Activity Status

## ◆ I2C_STATUS_MST_HOLD_RX_FIFO_FULL

#define I2C_STATUS_MST_HOLD_RX_FIFO_FULL (0x1U << 8)

XXX

## ◆ I2C_STATUS_MST_HOLD_TX_FIFO_EMPTY

#define I2C_STATUS_MST_HOLD_TX_FIFO_EMPTY (0x1U << 7)

XXX

## ◆ I2C_STATUS_RFF

#define I2C_STATUS_RFF (0x1U << 4)

Receive FIFO Completely Full

## ◆ I2C_STATUS_RFNE

#define I2C_STATUS_RFNE (0x1U << 3)

Receive FIFO Not Empty

## ◆ I2C_STATUS_SDA_STUCK_NOT_RECOVERED

#define I2C_STATUS_SDA_STUCK_NOT_RECOVERED (0x1U << 11)

XXX

## ◆ I2C_STATUS_SLV_ACTIVITY

#define I2C_STATUS_SLV_ACTIVITY (0x1U << 6)

Slave FSM Activity Status

## ◆ I2C_STATUS_SLV_HOLD_RX_FIFO_FULL

#define I2C_STATUS_SLV_HOLD_RX_FIFO_FULL (0x1U << 10)

XXX

## ◆ I2C_STATUS_SLV_HOLD_TX_FIFO_EMPTY

#define I2C_STATUS_SLV_HOLD_TX_FIFO_EMPTY (0x1U << 9)

XXX

## ◆ I2C_STATUS_SMBUS_ALERT_STATUS

#define I2C_STATUS_SMBUS_ALERT_STATUS (0x1U << 20)

This bit indicates whether the status of the input signal is smbus_alert_in_n

## ◆ I2C_STATUS_SMBUS_QUICK_CMD_BIT

#define I2C_STATUS_SMBUS_QUICK_CMD_BIT (0x1U << 16)

XXX

## ◆ I2C_STATUS_SMBUS_SLAVE_ADDR_RESOLVED

#define I2C_STATUS_SMBUS_SLAVE_ADDR_RESOLVED (0x1U << 18)

This bit indicates whether the SMBus Slave address (sar[6:0]) is Resolved by ARP Master

## ◆ I2C_STATUS_SMBUS_SLAVE_ADDR_VALID

#define I2C_STATUS_SMBUS_SLAVE_ADDR_VALID (0x1U << 17)

This bit indicates whether the SMBus Slave address (sar[6:0]) is valid or not

## ◆ I2C_STATUS_SMBUS_SUSPEND_STATUS

#define I2C_STATUS_SMBUS_SUSPEND_STATUS (0x1U << 19)

This bit indicates whether the status of the input signal is smbus_sus_in_n

## ◆ I2C_STATUS_TFE

#define I2C_STATUS_TFE (0x1U << 2)

Transmit FIFO Completely Empty

## ◆ I2C_STATUS_TFNF

#define I2C_STATUS_TFNF (0x1U << 1)

Transmit FIFO Not Full

## ◆ I2C_TAR_10BITADDR_MASTER

#define I2C_TAR_10BITADDR_MASTER (0x1U << 12)

This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master.

## ◆ I2C_TAR_DEVICE_ID

#define I2C_TAR_DEVICE_ID (0x1U << 13)

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in TAR[6:0] is to be performed by the i2c Master.

## ◆ I2C_TAR_GC_OR_START

#define I2C_TAR_GC_OR_START (0x1U << 10)

this bit indicates whether a General Call or START byte command is to be performed by the i2c.

## ◆ I2C_TAR_SMBUS_QUICK_CMD

#define I2C_TAR_SMBUS_QUICK_CMD (0x1U << 16)

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Quick command is to be performed by the i2c.

## ◆ I2C_TAR_SPECIAL

#define I2C_TAR_SPECIAL (0x1U << 11)

This bit indicates whether software performs a Device-ID, General Call or START BYTE command.

## ◆ I2C_TAR_TAR_Msk

#define I2C_TAR_TAR_Msk (0x3FFU)

target address field mask bit

## ◆ I2C_TX_ABRT_SOURCE_10ADDR1_NOACK

#define I2C_TX_ABRT_SOURCE_10ADDR1_NOACK (0x1U << 1)

Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.

## ◆ I2C_TX_ABRT_SOURCE_10ADDR2_NOACK

#define I2C_TX_ABRT_SOURCE_10ADDR2_NOACK (0x1U << 2)

Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave

## ◆ I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT

#define I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT (0x1U << 10)

XXX

## ◆ I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK

#define I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK (0x1U << 0)

Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave

## ◆ I2C_TX_ABRT_SOURCE_DEVICE_NOACK

#define I2C_TX_ABRT_SOURCE_DEVICE_NOACK (0x1U << 18)

XXX

## ◆ I2C_TX_ABRT_SOURCE_DEVICE_SLVADDR_NOACK

#define I2C_TX_ABRT_SOURCE_DEVICE_SLVADDR_NOACK (0x1U << 19)

XXX

## ◆ I2C_TX_ABRT_SOURCE_DEVICE_WRITE

#define I2C_TX_ABRT_SOURCE_DEVICE_WRITE (0x1U << 20)

XXX

## ◆ I2C_TX_ABRT_SOURCE_GCALL_NOACK

#define I2C_TX_ABRT_SOURCE_GCALL_NOACK (0x1U << 4)

XXX

## ◆ I2C_TX_ABRT_SOURCE_GCALL_READ

#define I2C_TX_ABRT_SOURCE_GCALL_READ (0x1U << 5)

XXX

## ◆ I2C_TX_ABRT_SOURCE_HS_ACKDET

#define I2C_TX_ABRT_SOURCE_HS_ACKDET (0x1U << 6)

XXX

## ◆ I2C_TX_ABRT_SOURCE_HS_NORSTRT

#define I2C_TX_ABRT_SOURCE_HS_NORSTRT (0x1U << 8)

XXX

## ◆ I2C_TX_ABRT_SOURCE_LOST

#define I2C_TX_ABRT_SOURCE_LOST (0x1U << 12)

XXX

## ◆ I2C_TX_ABRT_SOURCE_MASTER_DIS

#define I2C_TX_ABRT_SOURCE_MASTER_DIS (0x1U << 11)

XXX

## ◆ I2C_TX_ABRT_SOURCE_SBYTE_ACKDET

#define I2C_TX_ABRT_SOURCE_SBYTE_ACKDET (0x1U << 7)

XXX

## ◆ I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT

#define I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT (0x1U << 9)

XXX

## ◆ I2C_TX_ABRT_SOURCE_SDA_STUCK_AT_LOW

#define I2C_TX_ABRT_SOURCE_SDA_STUCK_AT_LOW (0x1U << 17)

XXX

## ◆ I2C_TX_ABRT_SOURCE_SLV_ARBLOST

#define I2C_TX_ABRT_SOURCE_SLV_ARBLOST (0x1U << 14)

XXX

## ◆ I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO

#define I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO (0x1U << 13)

XXX

## ◆ I2C_TX_ABRT_SOURCE_SLVRD_INTX

#define I2C_TX_ABRT_SOURCE_SLVRD_INTX (0x1U << 15)

XXX

## ◆ I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk

#define I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk (0xFF800000U)

XXX

## ◆ I2C_TX_ABRT_SOURCE_TXDATA_NOACK

#define I2C_TX_ABRT_SOURCE_TXDATA_NOACK (0x1U << 3)

XXX

## ◆ I2C_TX_ABRT_SOURCE_USER_ABRT

#define I2C_TX_ABRT_SOURCE_USER_ABRT (0x1U << 16)

XXX

## ◆ I2S_CCR_SCLKG_12

#define I2S_CCR_SCLKG_12 (0x1U << 0)

Gating after 12 sclk cycles

## ◆ I2S_CCR_SCLKG_16

#define I2S_CCR_SCLKG_16 (0x2U << 0)

Gating after 16 sclk cycles

## ◆ I2S_CCR_SCLKG_20

#define I2S_CCR_SCLKG_20 (0x3U << 0)

Gating after 20 sclk cycles

## ◆ I2S_CCR_SCLKG_24

#define I2S_CCR_SCLKG_24 (0x4U << 0)

Gating after 24 sclk cycles

## ◆ I2S_CCR_SCLKG_Msk

#define I2S_CCR_SCLKG_Msk (0x7U << 0)

Gating of sclk field mask

## ◆ I2S_CCR_SCLKG_NONE

#define I2S_CCR_SCLKG_NONE (0x0U << 0)

Clock gating is disabled

## ◆ I2S_CCR_WSS_16

#define I2S_CCR_WSS_16 (0x0U << 3)

16 sclk cycles

## ◆ I2S_CCR_WSS_24

#define I2S_CCR_WSS_24 (0x1U << 3)

24 sclk cycles

## ◆ I2S_CCR_WSS_32

#define I2S_CCR_WSS_32 (0x2U << 3)

32 sclk cycles

## ◆ I2S_CCR_WSS_Msk

#define I2S_CCR_WSS_Msk (0x3U << 3)

No description

## ◆ I2S_CER_CLKEN

#define I2S_CER_CLKEN (0x1U << 0)

Clock generation enable/disable

## ◆ I2S_IER_IEN

#define I2S_IER_IEN (0x1U << 0)

I2S Enable

## ◆ I2S_IRER_RXEN

#define I2S_IRER_RXEN (0x1U << 0)

Receiver block enable

## ◆ I2S_ITER_TXEN

#define I2S_ITER_TXEN (0x1U << 0)

Transmitter block enable

## ◆ I2S_RXFFR_RXFFR

#define I2S_RXFFR_RXFFR (0x1U << 0)

Receiver FIFO Reset

## ◆ I2S_TXFFR_TXFFR

#define I2S_TXFFR_TXFFR (0x1U << 0)

Transmitter FIFO Reset

## ◆ IWDG_KR_KEY

#define IWDG_KR_KEY ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

## ◆ IWDG_PR_PR

#define IWDG_PR_PR ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

## ◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0 ((uint8_t)0x01)

Bit 0

## ◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1 ((uint8_t)0x02)

Bit 1

## ◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2 ((uint8_t)0x04)

Bit 2

## ◆ IWDG_RLR_RL

#define IWDG_RLR_RL ((uint16_t)0x0FFF)

Watchdog counter reload value

## ◆ IWDG_SR_PVU

#define IWDG_SR_PVU ((uint8_t)0x01)

Watchdog prescaler value update

## ◆ IWDG_SR_RVU

#define IWDG_SR_RVU ((uint8_t)0x02)

Watchdog counter reload value update

## ◆ MHSI_VALUE

#define MHSI_VALUE (8000000)

Value of the Internal 8M oscillator in Hz

## ◆ PERIPH_BASE

#define PERIPH_BASE ((uint32_t)0x40000000UL)

Peripheral base address in the alias region

## ◆ PERIPH_BB_BASE

#define PERIPH_BB_BASE ((uint32_t)0x42000000UL)

Peripheral base address in the bit-band region

## ◆ PWR_CR0_DBP

#define PWR_CR0_DBP (0x1U << 0)

Disable Backup Domain write protection

## ◆ RTC_ALRH_RTC_ALR

#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF)

RTC Alarm High

## ◆ RTC_ALRL_RTC_ALR

#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF)

RTC Alarm Low

## ◆ RTC_CNTH_RTC_CNT

#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF)

RTC Counter High

## ◆ RTC_CNTL_RTC_CNT

#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF)

RTC Counter Low

## ◆ RTC_CRH_ALRIE

#define RTC_CRH_ALRIE ((uint8_t)0x02)

Alarm Interrupt Enable

## ◆ RTC_CRH_OWIE

#define RTC_CRH_OWIE ((uint8_t)0x04)

OverfloW Interrupt Enable

## ◆ RTC_CRH_SECIE

#define RTC_CRH_SECIE ((uint8_t)0x01)

Second Interrupt Enable

## ◆ RTC_CRL_ALRF

#define RTC_CRL_ALRF ((uint8_t)0x02)

Alarm Flag

## ◆ RTC_CRL_CNF

#define RTC_CRL_CNF ((uint8_t)0x10)

Configuration Flag

## ◆ RTC_CRL_OWF

#define RTC_CRL_OWF ((uint8_t)0x04)

OverfloW Flag

## ◆ RTC_CRL_RSF

#define RTC_CRL_RSF ((uint8_t)0x08)

Registers Synchronized Flag

## ◆ RTC_CRL_RTOFF

#define RTC_CRL_RTOFF ((uint8_t)0x20)

RTC operation OFF

## ◆ RTC_CRL_SECF

#define RTC_CRL_SECF ((uint8_t)0x01)

Second Flag

## ◆ RTC_DIVH_RTC_DIV

#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F)

RTC Clock Divider High

## ◆ RTC_DIVL_RTC_DIV

#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF)

RTC Clock Divider Low

## ◆ RTC_PRLH_PRL

#define RTC_PRLH_PRL ((uint16_t)0x000F)

RTC Prescaler Reload Value High

## ◆ RTC_PRLL_PRL

#define RTC_PRLL_PRL ((uint16_t)0xFFFF)

RTC Prescaler Reload Value Low

## ◆ SFM_CTRL_EXP_EN

#define SFM_CTRL_EXP_EN (0x1U << 3)

Bit Expand Function Enable Bit

## ◆ SFM_CTRL_EXP_RATE_1

#define SFM_CTRL_EXP_RATE_1 (0x0U << 0)

Bit Expand Rate 1

## ◆ SFM_CTRL_EXP_RATE_2

#define SFM_CTRL_EXP_RATE_2 (0x1U << 0)

Bit Expand Rate 2

## ◆ SFM_CTRL_EXP_RATE_3

#define SFM_CTRL_EXP_RATE_3 (0x2U << 0)

Bit Expand Rate 3

## ◆ SFM_CTRL_EXP_RATE_4

#define SFM_CTRL_EXP_RATE_4 (0x3U << 0)

Bit Expand Rate 4

## ◆ SFM_CTRL_EXP_RATE_5

#define SFM_CTRL_EXP_RATE_5 (0x4U << 0)

Bit Expand Rate 5

## ◆ SFM_CTRL_EXP_RATE_6

#define SFM_CTRL_EXP_RATE_6 (0x5U << 0)

Bit Expand Rate 6

## ◆ SFM_CTRL_EXP_RATE_7

#define SFM_CTRL_EXP_RATE_7 (0x6U << 0)

Bit Expand Rate 7

## ◆ SFM_CTRL_EXP_RATE_8

#define SFM_CTRL_EXP_RATE_8 (0x7U << 0)

Bit Expand Rate 8

## ◆ SFM_CTRL_EXP_RATE_Msk

#define SFM_CTRL_EXP_RATE_Msk (0x7U << 0)

Bit Expand Rate field mask bit

## ◆ SFM_USBPSDCSR_JSTATEN

#define SFM_USBPSDCSR_JSTATEN (0x1U << 9)

No description

## ◆ SFM_USBPSDCSR_JSTATF

#define SFM_USBPSDCSR_JSTATF (0x1U << 1)

No description

## ◆ SFM_USBPSDCSR_KSTATEN

#define SFM_USBPSDCSR_KSTATEN (0x1U << 10)

No description

## ◆ SFM_USBPSDCSR_KSTATF

#define SFM_USBPSDCSR_KSTATF (0x1U << 2)

No description

## ◆ SFM_USBPSDCSR_SE0EN

#define SFM_USBPSDCSR_SE0EN (0x1U << 8)

No description

## ◆ SFM_USBPSDCSR_SE0F

#define SFM_USBPSDCSR_SE0F (0x1U << 0)

No description

## ◆ SFM_USBPSDCSR_SE1EN

#define SFM_USBPSDCSR_SE1EN (0x1U << 11)

No description

## ◆ SFM_USBPSDCSR_SE1F

#define SFM_USBPSDCSR_SE1F (0x1U << 3)

No description

## ◆ SPI_BAUDR_SCKDV_Msk

#define SPI_BAUDR_SCKDV_Msk (0xFFFFU)

SPI Clock Divider field mask

## ◆ SPI_CR0_CFS_01_BIT

#define SPI_CR0_CFS_01_BIT (0x0U << 12)

1-bit Control Word

## ◆ SPI_CR0_CFS_02_BIT

#define SPI_CR0_CFS_02_BIT (0x1U << 12)

2-bit Control Word

## ◆ SPI_CR0_CFS_03_BIT

#define SPI_CR0_CFS_03_BIT (0x2U << 12)

3-bit Control Word

## ◆ SPI_CR0_CFS_04_BIT

#define SPI_CR0_CFS_04_BIT (0x3U << 12)

4-bit Control Word

## ◆ SPI_CR0_CFS_05_BIT

#define SPI_CR0_CFS_05_BIT (0x4U << 12)

5-bit Control Word

## ◆ SPI_CR0_CFS_06_BIT

#define SPI_CR0_CFS_06_BIT (0x5U << 12)

6-bit Control Word

## ◆ SPI_CR0_CFS_07_BIT

#define SPI_CR0_CFS_07_BIT (0x6U << 12)

7-bit Control Word

## ◆ SPI_CR0_CFS_08_BIT

#define SPI_CR0_CFS_08_BIT (0x7U << 12)

8-bit Control Word

## ◆ SPI_CR0_CFS_09_BIT

#define SPI_CR0_CFS_09_BIT (0x8U << 12)

9-bit Control Word

## ◆ SPI_CR0_CFS_10_BIT

#define SPI_CR0_CFS_10_BIT (0x9U << 12)

10-bit Control Word

## ◆ SPI_CR0_CFS_11_BIT

#define SPI_CR0_CFS_11_BIT (0xAU << 12)

11-bit Control Word

## ◆ SPI_CR0_CFS_12_BIT

#define SPI_CR0_CFS_12_BIT (0xBU << 12)

12-bit Control Word

## ◆ SPI_CR0_CFS_13_BIT

#define SPI_CR0_CFS_13_BIT (0xCU << 12)

13-bit Control Word

## ◆ SPI_CR0_CFS_14_BIT

#define SPI_CR0_CFS_14_BIT (0xDU << 12)

14-bit Control Word

## ◆ SPI_CR0_CFS_15_BIT

#define SPI_CR0_CFS_15_BIT (0xEU << 12)

15-bit Control Word

## ◆ SPI_CR0_CFS_16_BIT

#define SPI_CR0_CFS_16_BIT (0xFU << 12)

16-bit Control Word

## ◆ SPI_CR0_CFS_Msk

#define SPI_CR0_CFS_Msk (0xFU << 12)

Control Frame Size field mask

## ◆ SPI_CR0_CPHA

#define SPI_CR0_CPHA (0x1U << 6)

Serial Clock Phase

## ◆ SPI_CR0_CPOL

#define SPI_CR0_CPOL (0x1U << 7)

Serial Clock Polarity

## ◆ SPI_CR0_DFS_10BITS

#define SPI_CR0_DFS_10BITS (0x9U << 0)

10-bit serial data transfer

## ◆ SPI_CR0_DFS_11BITS

#define SPI_CR0_DFS_11BITS (0xAU << 0)

11-bit serial data transfer

## ◆ SPI_CR0_DFS_12BITS

#define SPI_CR0_DFS_12BITS (0xBU << 0)

12-bit serial data transfer

## ◆ SPI_CR0_DFS_13BITS

#define SPI_CR0_DFS_13BITS (0xCU << 0)

13-bit serial data transfer

## ◆ SPI_CR0_DFS_14BITS

#define SPI_CR0_DFS_14BITS (0xDU << 0)

14-bit serial data transfer

## ◆ SPI_CR0_DFS_15BITS

#define SPI_CR0_DFS_15BITS (0xEU << 0)

15-bit serial data transfer

## ◆ SPI_CR0_DFS_16BITS

#define SPI_CR0_DFS_16BITS (0xFU << 0)

16-bit serial data transfer

## ◆ SPI_CR0_DFS_4BITS

#define SPI_CR0_DFS_4BITS (0x3U << 0)

4-bit serial data transfer

## ◆ SPI_CR0_DFS_5BITS

#define SPI_CR0_DFS_5BITS (0x4U << 0)

5-bit serial data transfer

## ◆ SPI_CR0_DFS_6BITS

#define SPI_CR0_DFS_6BITS (0x5U << 0)

6-bit serial data transfer

## ◆ SPI_CR0_DFS_7BITS

#define SPI_CR0_DFS_7BITS (0x6U << 0)

7-bit serial data transfer

## ◆ SPI_CR0_DFS_8BITS

#define SPI_CR0_DFS_8BITS (0x7U << 0)

8-bit serial data transfer

## ◆ SPI_CR0_DFS_9BITS

#define SPI_CR0_DFS_9BITS (0x8U << 0)

9-bit serial data transfer

## ◆ SPI_CR0_DFS_Msk

#define SPI_CR0_DFS_Msk (0xFU << 0)

Data Frame Size field mask

## ◆ SPI_CR0_FRF_Msk

#define SPI_CR0_FRF_Msk (0x3U << 4)

Frame Format field mask

## ◆ SPI_CR0_FRF_NS

#define SPI_CR0_FRF_NS (0x2U << 4)

National Microwire Frame Format

## ◆ SPI_CR0_FRF_SPI

#define SPI_CR0_FRF_SPI (0x0U << 4)

Motorolla SPI Frame Format

## ◆ SPI_CR0_FRF_SSP

#define SPI_CR0_FRF_SSP (0x1U << 4)

Texas Instruments SSP Frame Format

## ◆ SPI_CR0_SLV_OE

#define SPI_CR0_SLV_OE (0x1U << 10)

Slave Output Enable

## ◆ SPI_CR0_SPI_MODE_DUAL

#define SPI_CR0_SPI_MODE_DUAL (0x1U << 21)

Dual SPI Mode

## ◆ SPI_CR0_SPI_MODE_Msk

#define SPI_CR0_SPI_MODE_Msk (0x3U << 21)

SPI Mode field mask

## ◆ SPI_CR0_SPI_MODE_OCTAL

#define SPI_CR0_SPI_MODE_OCTAL (0x3U << 21)

Octal SPI Mode

## ◆ SPI_CR0_SPI_MODE_QUAD

#define SPI_CR0_SPI_MODE_QUAD (0x2U << 21)

Quad SPI Mode

## ◆ SPI_CR0_SPI_MODE_STD

#define SPI_CR0_SPI_MODE_STD (0x0U << 21)

Standard SPI Mode

## ◆ SPI_CR0_SRL

#define SPI_CR0_SRL (0x1U << 11)

Shift Register Loop

## ◆ SPI_CR0_SSTE

#define SPI_CR0_SSTE (0x1U << 24)

Slave Select Toggle Enable

## ◆ SPI_CR0_TMOD_EEPROM_READ

#define SPI_CR0_TMOD_EEPROM_READ (0x3U << 8)

EEPROM Read mode

## ◆ SPI_CR0_TMOD_Msk

#define SPI_CR0_TMOD_Msk (0x3U << 8)

Transfer Mode field mask

## ◆ SPI_CR0_TMOD_RX_ONLY

#define SPI_CR0_TMOD_RX_ONLY (0x2U << 8)

Receive only mode

## ◆ SPI_CR0_TMOD_TX_AND_RX

#define SPI_CR0_TMOD_TX_AND_RX (0x0U << 8)

Transfer & receive

## ◆ SPI_CR0_TMOD_TX_ONLY

#define SPI_CR0_TMOD_TX_ONLY (0x1U << 8)

Transmit only mode

## ◆ SPI_CR1_NDF_Msk

#define SPI_CR1_NDF_Msk (0xFFFFU)

Number of Data Frames field mask

## ◆ SPI_DMACR_RDMAE

#define SPI_DMACR_RDMAE (0x1U << 0)

Receive DMA Enable

## ◆ SPI_DMACR_TDMAE

#define SPI_DMACR_TDMAE (0x1U << 1)

Transmit DMA Enable

## ◆ SPI_ESPICR_ADDRL_0BIT

#define SPI_ESPICR_ADDRL_0BIT (0x0U << 2)

0-bit Address Width

## ◆ SPI_ESPICR_ADDRL_12BIT

#define SPI_ESPICR_ADDRL_12BIT (0x3U << 2)

12-bit Address Width

## ◆ SPI_ESPICR_ADDRL_16BIT

#define SPI_ESPICR_ADDRL_16BIT (0x4U << 2)

16-bit Address Width

## ◆ SPI_ESPICR_ADDRL_20BIT

#define SPI_ESPICR_ADDRL_20BIT (0x5U << 2)

20-bit Address Width

## ◆ SPI_ESPICR_ADDRL_24BIT

#define SPI_ESPICR_ADDRL_24BIT (0x6U << 2)

24-bit Address Width

## ◆ SPI_ESPICR_ADDRL_28BIT

#define SPI_ESPICR_ADDRL_28BIT (0x7U << 2)

28-bit Address Width

## ◆ SPI_ESPICR_ADDRL_32BIT

#define SPI_ESPICR_ADDRL_32BIT (0x8U << 2)

32-bit Address Width

## ◆ SPI_ESPICR_ADDRL_36BIT

#define SPI_ESPICR_ADDRL_36BIT (0x9U << 2)

36-bit Address Width

## ◆ SPI_ESPICR_ADDRL_40BIT

#define SPI_ESPICR_ADDRL_40BIT (0xAU << 2)

40-bit Address Width

## ◆ SPI_ESPICR_ADDRL_44BIT

#define SPI_ESPICR_ADDRL_44BIT (0xBU << 2)

44-bit Address Width

## ◆ SPI_ESPICR_ADDRL_48BIT

#define SPI_ESPICR_ADDRL_48BIT (0xCU << 2)

48-bit Address Width

## ◆ SPI_ESPICR_ADDRL_4BIT

#define SPI_ESPICR_ADDRL_4BIT (0x1U << 2)

4-bit Address Width

## ◆ SPI_ESPICR_ADDRL_52BIT

#define SPI_ESPICR_ADDRL_52BIT (0xDU << 2)

52-bit Address Width

## ◆ SPI_ESPICR_ADDRL_56BIT

#define SPI_ESPICR_ADDRL_56BIT (0xEU << 2)

56-bit Address Width

## ◆ SPI_ESPICR_ADDRL_60BIT

#define SPI_ESPICR_ADDRL_60BIT (0xFU << 2)

60-bit Address Width

## ◆ SPI_ESPICR_ADDRL_8BIT

#define SPI_ESPICR_ADDRL_8BIT (0x2U << 2)

8-bit Address Width

## ◆ SPI_ESPICR_ADDRL_Msk

#define SPI_ESPICR_ADDRL_Msk (0xFU << 2)

Address Length field mask

## ◆ SPI_ESPICR_INSTL_0BIT

#define SPI_ESPICR_INSTL_0BIT (0x0U << 8)

0-bit (No Instruction)

## ◆ SPI_ESPICR_INSTL_16BIT

#define SPI_ESPICR_INSTL_16BIT (0x3U << 8)

16-bit Instruction

## ◆ SPI_ESPICR_INSTL_4BIT

#define SPI_ESPICR_INSTL_4BIT (0x1U << 8)

4-bit Instruction

## ◆ SPI_ESPICR_INSTL_8BIT

#define SPI_ESPICR_INSTL_8BIT (0x2U << 8)

8-bit Instruction

## ◆ SPI_ESPICR_INSTL_Msk

#define SPI_ESPICR_INSTL_Msk (0x3U << 8)

Instruction Length field mask

## ◆ SPI_ESPICR_TRANST_Msk

#define SPI_ESPICR_TRANST_Msk (0x3U << 0)

Address and instruction transfer format field mask

## ◆ SPI_ESPICR_WCYC_Msk

#define SPI_ESPICR_WCYC_Msk (0x1FU << 11)

Wait cycles field mask

## ◆ SPI_IER_MSTIE

#define SPI_IER_MSTIE (0x1U << 5)

Multi-Master Contention Interrupt Enable

## ◆ SPI_IER_RXFIE

#define SPI_IER_RXFIE (0x1U << 4)

Receive FIFO Full Interrupt Enable

## ◆ SPI_IER_RXOIE

#define SPI_IER_RXOIE (0x1U << 3)

Receive FIFO Overflow Interrupt Enable

## ◆ SPI_IER_RXUIE

#define SPI_IER_RXUIE (0x1U << 2)

Receive FIFO Underflow Interrupt Enable

## ◆ SPI_IER_TXEIE

#define SPI_IER_TXEIE (0x1U << 0)

Transmit FIFO Empty Interrupt Enable

## ◆ SPI_IER_TXOIE

#define SPI_IER_TXOIE (0x1U << 1)

Transmit FIFO Overflow Interrupt Enable

## ◆ SPI_ISR_MSTIS

#define SPI_ISR_MSTIS (0x1U << 5)

Multi-Master Contention Interrupt Status

## ◆ SPI_ISR_RXFIS

#define SPI_ISR_RXFIS (0x1U << 4)

Receive FIFO Full Interrupt Status

## ◆ SPI_ISR_RXOIS

#define SPI_ISR_RXOIS (0x1U << 3)

Receive FIFO Overflow Interrupt Status

## ◆ SPI_ISR_RXUIS

#define SPI_ISR_RXUIS (0x1U << 2)

Receive FIFO Underflow Interrupt Status

## ◆ SPI_ISR_TXEIS

#define SPI_ISR_TXEIS (0x1U << 0)

Transmit FIFO Empty Interrupt Status

## ◆ SPI_ISR_TXOIS

#define SPI_ISR_TXOIS (0x1U << 1)

Transmit FIFO Overflow Interrupt Status

## ◆ SPI_MWCR_MDD

#define SPI_MWCR_MDD (0x1U << 1)

Microwire Control

## ◆ SPI_MWCR_MHS

#define SPI_MWCR_MHS (0x1U << 2)

Microwire Handshaking

## ◆ SPI_MWCR_MWMOD

#define SPI_MWCR_MWMOD (0x1U << 0)

Microwire Transfer Mode

## ◆ SPI_RISR_MSTIR

#define SPI_RISR_MSTIR (0x1U << 5)

Multi-Master Contention Raw Interrupt Status

## ◆ SPI_RISR_RXFIR

#define SPI_RISR_RXFIR (0x1U << 4)

Receive FIFO Full Raw Interrupt Status

## ◆ SPI_RISR_RXOIR

#define SPI_RISR_RXOIR (0x1U << 3)

Receive FIFO Overflow Raw Interrupt Status

## ◆ SPI_RISR_RXUIR

#define SPI_RISR_RXUIR (0x1U << 2)

Receive FIFO Underflow Raw Interrupt Status

## ◆ SPI_RISR_TXEIR

#define SPI_RISR_TXEIR (0x1U << 0)

Transmit FIFO Empty Raw Interrupt Status

## ◆ SPI_RISR_TXOIR

#define SPI_RISR_TXOIR (0x1U << 1)

Transmit FIFO Overflow Raw Interrupt Status

## ◆ SPI_SER_Msk

#define SPI_SER_Msk (0x7U << 0)

Slave Select Enable Flag field mask

## ◆ SPI_SER_SE0

#define SPI_SER_SE0 (0x1U << 0)

Slave 0 Select Enable Flag

## ◆ SPI_SER_SE1

#define SPI_SER_SE1 (0x1U << 1)

Slave 1 Select Enable Flag

## ◆ SPI_SER_SE2

#define SPI_SER_SE2 (0x1U << 2)

Slave 2 Select Enable Flag

## ◆ SPI_SPIENR_SPI_EN

#define SPI_SPIENR_SPI_EN (0x1U << 0)

SPI Enable

## ◆ SPI_SR_BUSY

#define SPI_SR_BUSY (0x1U << 0)

SPI Busy Flag

## ◆ SPI_SR_DCOL

#define SPI_SR_DCOL (0x1U << 6)

Data Collision Error

## ◆ SPI_SR_RFF

#define SPI_SR_RFF (0x1U << 4)

Receive FIFO Full

## ◆ SPI_SR_RFNE

#define SPI_SR_RFNE (0x1U << 3)

Receive FIFO Not Empty

## ◆ SPI_SR_TFE

#define SPI_SR_TFE (0x1U << 2)

Transmit FIFO Empty

## ◆ SPI_SR_TFNF

#define SPI_SR_TFNF (0x1U << 1)

Transmit FIFO Not Full

## ◆ SPI_SR_TXERR

#define SPI_SR_TXERR (0x1U << 5)

Transmission Error

## ◆ SRAM_BASE

#define SRAM_BASE ((uint32_t)0x20000000UL)

SRAM base address in the alias region

## ◆ SRAM_BB_BASE

#define SRAM_BB_BASE ((uint32_t)0x22000000UL)

SRAM base address in the bit-band region

## ◆ TIM_ARR_ARR

#define TIM_ARR_ARR (0xFFFFFU)

actual auto-reload Value

## ◆ TIM_BDTR_AOE

#define TIM_BDTR_AOE (0x1U << 14)

Automatic Output enable

## ◆ TIM_BDTR_BKE

#define TIM_BDTR_BKE (0x1U << 12)

Break enable

## ◆ TIM_BDTR_BKP

#define TIM_BDTR_BKP (0x1U << 13)

Break Polarity

## ◆ TIM_BDTR_DTG

#define TIM_BDTR_DTG (0xFFU << 0)

DTG[0:7] bits (Dead-Time Generator set-up)

## ◆ TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_0 (0x1U << 0)

Bit 0

## ◆ TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_1 (0x1U << 1)

Bit 1

## ◆ TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_2 (0x1U << 2)

Bit 2

## ◆ TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_3 (0x1U << 3)

Bit 3

## ◆ TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_4 (0x1U << 4)

Bit 4

## ◆ TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_5 (0x1U << 5)

Bit 5

## ◆ TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_6 (0x1U << 6)

Bit 6

## ◆ TIM_BDTR_DTG_7

#define TIM_BDTR_DTG_7 (0x1U << 7)

Bit 7

## ◆ TIM_BDTR_LOCK

#define TIM_BDTR_LOCK (0x3U << 8)

LOCK[1:0] bits (Lock Configuration)

## ◆ TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_0 (0x1U << 8)

Bit 0

## ◆ TIM_BDTR_LOCK_1

#define TIM_BDTR_LOCK_1 (0x1U << 9)

Bit 1

## ◆ TIM_BDTR_MOE

#define TIM_BDTR_MOE (0x1U << 15)

Main Output enable

## ◆ TIM_BDTR_OSSI

#define TIM_BDTR_OSSI (0x1U << 10)

Off-State Selection for Idle mode

## ◆ TIM_BDTR_OSSR

#define TIM_BDTR_OSSR (0x1U << 11)

Off-State Selection for Run mode

## ◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E (0x1U << 0)

Capture/Compare 1 output enable

## ◆ TIM_CCER_CC1NE

#define TIM_CCER_CC1NE (0x1U << 2)

Capture/Compare 1 Complementary output enable

## ◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP (0x1U << 3)

Capture/Compare 1 Complementary output Polarity

## ◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P (0x1U << 1)

Capture/Compare 1 output Polarity

## ◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E (0x1U << 4)

Capture/Compare 2 output enable

## ◆ TIM_CCER_CC2NE

#define TIM_CCER_CC2NE (0x1U << 6)

Capture/Compare 2 Complementary output enable

## ◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP (0x1U << 7)

Capture/Compare 2 Complementary output Polarity

## ◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P (0x1U << 5)

Capture/Compare 2 output Polarity

## ◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E (0x1U << 8)

Capture/Compare 3 output enable

## ◆ TIM_CCER_CC3NE

#define TIM_CCER_CC3NE (0x1U << 10)

Capture/Compare 3 Complementary output enable

## ◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP (0x1U << 11)

Capture/Compare 3 Complementary output Polarity

## ◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P (0x1U << 9)

Capture/Compare 3 output Polarity

## ◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E (0x1U << 12)

Capture/Compare 4 output enable

## ◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P (0x1U << 13)

Capture/Compare 4 output Polarity

## ◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S (0x3U << 0)

CC1S[1:0] bits (Capture/Compare 1 Selection)

## ◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0 (0x1U << 0)

Bit 0

## ◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1 (0x1U << 1)

Bit 1

## ◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S (0x3U << 8)

CC2S[1:0] bits (Capture/Compare 2 Selection)

## ◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0 (0x1U << 8)

Bit 0

## ◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1 (0x1U << 9)

Bit 1

## ◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F (0xFU << 4)

IC1F[3:0] bits (Input Capture 1 Filter)

## ◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0 (0x1U << 4)

Bit 0

## ◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1 (0x1U << 5)

Bit 1

## ◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2 (0x1U << 6)

Bit 2

## ◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3 (0x1U << 7)

Bit 3

## ◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC (0x3U << 2)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

## ◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0 (0x1U << 2)

Bit 0

## ◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1 (0x1U << 3)

Bit 1

## ◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F (0xFU << 12)

IC2F[3:0] bits (Input Capture 2 Filter)

## ◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0 (0x1U << 12)

Bit 0

## ◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1 (0x1U << 13)

Bit 1

## ◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2 (0x1U << 14)

Bit 2

## ◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3 (0x1U << 15)

Bit 3

## ◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC (0x3U << 10)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

## ◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0 (0x1U << 10)

Bit 0

## ◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1 (0x1U << 11)

Bit 1

## ◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE (0x1U << 7)

Output Compare 1 Clear Enable

## ◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE (0x1U << 2)

Output Compare 1 Fast enable

## ◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M (0x7U << 4)

OC1M[2:0] bits (Output Compare 1 Mode)

## ◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0 (0x1U << 4)

Bit 0

## ◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1 (0x1U << 5)

Bit 1

## ◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2 (0x1U << 6)

Bit 2

## ◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE (0x1U << 3)

Output Compare 1 Preload enable

## ◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE (0x1U << 15)

Output Compare 2 Clear Enable

## ◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE (0x1U << 10)

Output Compare 2 Fast enable

## ◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M (0x7U << 12)

OC2M[2:0] bits (Output Compare 2 Mode)

## ◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0 (0x1U << 12)

Bit 0

## ◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1 (0x1U << 13)

Bit 1

## ◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2 (0x1U << 14)

Bit 2

## ◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE (0x1U << 11)

Output Compare 2 Preload enable

## ◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S (0x3U << 0)

CC3S[1:0] bits (Capture/Compare 3 Selection)

## ◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0 (0x1U << 0)

Bit 0

## ◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1 (0x1U << 1)

Bit 1

## ◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S (0x3U << 8)

CC4S[1:0] bits (Capture/Compare 4 Selection)

## ◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0 (0x1U << 8)

Bit 0

## ◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1 (0x1U << 9)

Bit 1

## ◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F (0xFU << 4)

IC3F[3:0] bits (Input Capture 3 Filter)

## ◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0 (0x1U << 4)

Bit 0

## ◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1 (0x1U << 5)

Bit 1

## ◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2 (0x1U << 6)

Bit 2

## ◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3 (0x1U << 7)

Bit 3

## ◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC (0x3U << 2)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

## ◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0 (0x1U << 2)

Bit 0

## ◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1 (0x1U << 3)

Bit 1

## ◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F (0xFU << 12)

IC4F[3:0] bits (Input Capture 4 Filter)

## ◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0 (0x1U << 12)

Bit 0

## ◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1 (0x1U << 13)

Bit 1

## ◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2 (0x1U << 14)

Bit 2

## ◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3 (0x1U << 15)

Bit 3

## ◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC (0x3U << 10)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

## ◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0 (0x1U << 10)

Bit 0

## ◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1 (0x1U << 11)

Bit 1

## ◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE (0x1U << 7)

Output Compare 3 Clear Enable

## ◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE (0x1U << 2)

Output Compare 3 Fast enable

## ◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M (0x7U << 4)

OC3M[2:0] bits (Output Compare 3 Mode)

## ◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0 (0x1U << 4)

Bit 0

## ◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1 (0x1U << 5)

Bit 1

## ◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2 (0x1U << 6)

Bit 2

## ◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE (0x1U << 3)

Output Compare 3 Preload enable

## ◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE (0x1U << 15)

Output Compare 4 Clear Enable

## ◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE (0x1U << 10)

Output Compare 4 Fast enable

## ◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M (0x7U << 12)

OC4M[2:0] bits (Output Compare 4 Mode)

## ◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0 (0x1U << 12)

Bit 0

## ◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1 (0x1U << 13)

Bit 1

## ◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2 (0x1U << 14)

Bit 2

## ◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE (0x1U << 11)

Output Compare 4 Preload enable

## ◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1 (0xFFFFFU)

Capture/Compare 1 Value

## ◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2 (0xFFFFFU)

Capture/Compare 2 Value

## ◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3 (0xFFFFFU)

Capture/Compare 3 Value

## ◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4 (0xFFFFFU)

Capture/Compare 4 Value

## ◆ TIM_CNT_CNT

#define TIM_CNT_CNT (0xFFFFFU)

Counter Value

## ◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE (0x1U << 7)

Auto-reload preload enable

## ◆ TIM_CR1_CEN

#define TIM_CR1_CEN (0x1U << 0)

Counter enable

## ◆ TIM_CR1_CKD

#define TIM_CR1_CKD (0x3U << 8)

CKD[1:0] bits (clock division)

## ◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0 (0x1U << 8)

Bit 0

## ◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1 (0x1U << 9)

Bit 1

## ◆ TIM_CR1_CMS

#define TIM_CR1_CMS (0x3U << 5)

CMS[1:0] bits (Center-aligned mode selection)

## ◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0 (0x1U << 5)

Bit 0

## ◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1 (0x1U << 6)

Bit 1

## ◆ TIM_CR1_DIR

#define TIM_CR1_DIR (0x1U << 4)

Direction

## ◆ TIM_CR1_OPM

#define TIM_CR1_OPM (0x1U << 3)

One pulse mode

## ◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS (0x1U << 1)

Update disable

## ◆ TIM_CR1_URS

#define TIM_CR1_URS (0x1U << 2)

Update request source

## ◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS (0x1U << 3)

Capture/Compare DMA Selection

## ◆ TIM_CR2_CCPC

#define TIM_CR2_CCPC (0x1U << 0)

Capture/Compare Preloaded Control

## ◆ TIM_CR2_CCUS

#define TIM_CR2_CCUS (0x1U << 2)

Capture/Compare Control Update Selection

## ◆ TIM_CR2_MMS

#define TIM_CR2_MMS (0x7U << 4)

MMS[2:0] bits (Master Mode Selection)

## ◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0 (0x1U << 4)

Bit 0

## ◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1 (0x1U << 5)

Bit 1

## ◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2 (0x1U << 6)

Bit 2

## ◆ TIM_CR2_OIS1

#define TIM_CR2_OIS1 (0x1U << 8)

Output Idle state 1 (OC1 output)

## ◆ TIM_CR2_OIS1N

#define TIM_CR2_OIS1N (0x1U << 9)

Output Idle state 1 (OC1N output)

## ◆ TIM_CR2_OIS2

#define TIM_CR2_OIS2 (0x1U << 10)

Output Idle state 2 (OC2 output)

## ◆ TIM_CR2_OIS2N

#define TIM_CR2_OIS2N (0x1U << 11)

Output Idle state 2 (OC2N output)

## ◆ TIM_CR2_OIS3

#define TIM_CR2_OIS3 (0x1U << 12)

Output Idle state 3 (OC3 output)

## ◆ TIM_CR2_OIS3N

#define TIM_CR2_OIS3N (0x1U << 13)

Output Idle state 3 (OC3N output)

## ◆ TIM_CR2_OIS4

#define TIM_CR2_OIS4 (0x1U << 14)

Output Idle state 4 (OC4 output)

## ◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S (0x1U << 7)

TI1 Selection

## ◆ TIM_DIER_BIE

#define TIM_DIER_BIE (0x1U << 7)

Break interrupt enable

## ◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE (0x1U << 9)

Capture/Compare 1 DMA request enable

## ◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE (0x1U << 1)

Capture/Compare 1 interrupt enable

## ◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE (0x1U << 10)

Capture/Compare 2 DMA request enable

## ◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE (0x1U << 2)

Capture/Compare 2 interrupt enable

## ◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE (0x1U << 11)

Capture/Compare 3 DMA request enable

## ◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE (0x1U << 3)

Capture/Compare 3 interrupt enable

## ◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE (0x1U << 12)

Capture/Compare 4 DMA request enable

## ◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE (0x1U << 4)

Capture/Compare 4 interrupt enable

## ◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE (0x1U << 13)

COM DMA request enable

## ◆ TIM_DIER_COMIE

#define TIM_DIER_COMIE (0x1U << 5)

COM interrupt enable

## ◆ TIM_DIER_TDE

#define TIM_DIER_TDE (0x1U << 14)

Trigger DMA request enable

## ◆ TIM_DIER_TIE

#define TIM_DIER_TIE (0x1U << 6)

Trigger interrupt enable

## ◆ TIM_DIER_UDE

#define TIM_DIER_UDE (0x1U << 8)

Update DMA request enable

## ◆ TIM_DIER_UIE

#define TIM_DIER_UIE (0x1U << 0)

Update interrupt enable

## ◆ TIM_EGR_BG

#define TIM_EGR_BG (0x1U << 7)

Break Generation

## ◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G (0x1U << 1)

Capture/Compare 1 Generation

## ◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G (0x1U << 2)

Capture/Compare 2 Generation

## ◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G (0x1U << 3)

Capture/Compare 3 Generation

## ◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G (0x1U << 4)

Capture/Compare 4 Generation

## ◆ TIM_EGR_COMG

#define TIM_EGR_COMG (0x1U << 5)

Capture/Compare Control Update Generation

## ◆ TIM_EGR_TG

#define TIM_EGR_TG (0x1U << 6)

Trigger Generation

## ◆ TIM_EGR_UG

#define TIM_EGR_UG (0x1U << 0)

Update Generation

## ◆ TIM_PSC_PSC

#define TIM_PSC_PSC (0xFFFFU)

Prescaler Value

## ◆ TIM_RCR_REP

#define TIM_RCR_REP (0xFFU)

Repetition Counter Value

## ◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE (0x1U << 14)

External clock enable

## ◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF (0xFU << 8)

ETF[3:0] bits (External trigger filter)

## ◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0 (0x1U << 8)

Bit 0

## ◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1 (0x1U << 9)

Bit 1

## ◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2 (0x1U << 10)

Bit 2

## ◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3 (0x1U << 11)

Bit 3

## ◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP (0x1U << 15)

External trigger polarity

## ◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS (0x3U << 12)

ETPS[1:0] bits (External trigger prescaler)

## ◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0 (0x1U << 12)

Bit 0

## ◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1 (0x1U << 13)

Bit 1

## ◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM (0x1U << 7)

Master/slave mode

## ◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS (0x7U << 0)

SMS[2:0] bits (Slave mode selection)

## ◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0 (0x1U << 0)

Bit 0

## ◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1 (0x1U << 1)

Bit 1

## ◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2 (0x1U << 2)

Bit 2

## ◆ TIM_SMCR_TS

#define TIM_SMCR_TS (0x7U << 4)

TS[2:0] bits (Trigger selection)

## ◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0 (0x1U << 4)

Bit 0

## ◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1 (0x1U << 5)

Bit 1

## ◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2 (0x1U << 6)

Bit 2

## ◆ TIM_SR_BIF

#define TIM_SR_BIF (0x1U << 7)

Break interrupt Flag

## ◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF (0x1U << 1)

Capture/Compare 1 interrupt Flag

## ◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF (0x1U << 9)

Capture/Compare 1 Overcapture Flag

## ◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF (0x1U << 2)

Capture/Compare 2 interrupt Flag

## ◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF (0x1U << 10)

Capture/Compare 2 Overcapture Flag

## ◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF (0x1U << 3)

Capture/Compare 3 interrupt Flag

## ◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF (0x1U << 11)

Capture/Compare 3 Overcapture Flag

## ◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF (0x1U << 4)

Capture/Compare 4 interrupt Flag

## ◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF (0x1U << 12)

Capture/Compare 4 Overcapture Flag

## ◆ TIM_SR_COMIF

#define TIM_SR_COMIF (0x1U << 5)

COM interrupt Flag

## ◆ TIM_SR_TIF

#define TIM_SR_TIF (0x1U << 6)

Trigger interrupt Flag

## ◆ TIM_SR_UIF

#define TIM_SR_UIF (0x1U << 0)

Update interrupt Flag

## ◆ UART_DMASA

#define UART_DMASA (0x1U << 0)

DMA Software Acknowledge

## ◆ UART_EXTLCR_ADDR_MATCH

#define UART_EXTLCR_ADDR_MATCH (0x1U << 1)

Address Match Mode

## ◆ UART_EXTLCR_SEND_ADDR

#define UART_EXTLCR_SEND_ADDR (0x1U << 2)

Send address control bit

## ◆ UART_EXTLCR_TRANSMIT_MODE

#define UART_EXTLCR_TRANSMIT_MODE (0x1U << 3)

Transmit mode control bit

## ◆ UART_EXTLCR_WLS_E

#define UART_EXTLCR_WLS_E (0x1U << 0)

This bit is used to enable 9-bit data for transmit and receive transfers

## ◆ UART_FCR_FIFOE

#define UART_FCR_FIFOE (0x1U << 0)

FIFO Enable

## ◆ UART_FCR_RFIFOR

#define UART_FCR_RFIFOR (0x1U << 1)

RCVR FIFO Reset

## ◆ UART_FCR_RT_1

#define UART_FCR_RT_1 (0x0U << 6)

1 character in the FIFO

## ◆ UART_FCR_RT_14

#define UART_FCR_RT_14 (0x3U << 6)

FIFO 2 less than full

## ◆ UART_FCR_RT_4

#define UART_FCR_RT_4 (0x1U << 6)

FIFO 1/4 full

## ◆ UART_FCR_RT_8

#define UART_FCR_RT_8 (0x2U << 6)

FIFO 1/2 full

## ◆ UART_FCR_TET_0

#define UART_FCR_TET_0 (0x0U << 4)

FIFO empty

## ◆ UART_FCR_TET_2

#define UART_FCR_TET_2 (0x1U << 4)

2 characters in the FIFO

## ◆ UART_FCR_TET_4

#define UART_FCR_TET_4 (0x2U << 4)

FIFO 1/4 full

## ◆ UART_FCR_TET_8

#define UART_FCR_TET_8 (0x3U << 4)

FIFO 1/2 full

## ◆ UART_FCR_XFIFOR

#define UART_FCR_XFIFOR (0x1U << 2)

XMIT FIFO Reset

## ◆ UART_HTX_HTX

#define UART_HTX_HTX (0x1U << 0)

Halt TX

## ◆ UART_IER_LSRCLRMD

#define UART_IER_LSRCLRMD (0x1U << 4)

Controls the method for clearing the status in the LSR register

## ◆ UART_IER_MSIE

#define UART_IER_MSIE (0x1U << 3)

Modem Status Interrupt Enable

## ◆ UART_IER_PTIME

#define UART_IER_PTIME (0x1U << 7)

Programmable THRE Interrupt Mode Enable

## ◆ UART_IER_RDAIE

#define UART_IER_RDAIE (0x1U << 0)

Received Data Available Interrupt Enable

## ◆ UART_IER_RLSIE

#define UART_IER_RLSIE (0x1U << 2)

Receiver Line Status Interrupt Enable

## ◆ UART_IER_THREIE

#define UART_IER_THREIE (0x1U << 1)

Transmit Holding Register Empty Interrupt Enable

## ◆ UART_IIR_INTID_BUSY

#define UART_IIR_INTID_BUSY (0x7U)

Busy detect

## ◆ UART_IIR_INTID_CTI

#define UART_IIR_INTID_CTI (0xCU)

character timeout indicator

## ◆ UART_IIR_INTID_MSI

#define UART_IIR_INTID_MSI (0x0U)

Modem status interrupt

## ◆ UART_IIR_INTID_Msk

#define UART_IIR_INTID_Msk (0xFU)

Interrupt ID bit mask

## ◆ UART_IIR_INTID_NONE

#define UART_IIR_INTID_NONE (0x1U)

No interrupt pending

## ◆ UART_IIR_INTID_RDA

#define UART_IIR_INTID_RDA (0x4U)

Received data available interrupt

## ◆ UART_IIR_INTID_RLS

#define UART_IIR_INTID_RLS (0x6U)

Receiver line status interrupt

## ◆ UART_IIR_INTID_THRE

#define UART_IIR_INTID_THRE (0x2U)

Transmitter holding register empty

## ◆ UART_LCR_BC

#define UART_LCR_BC (0x1U << 6)

Break Control Bit

## ◆ UART_LCR_DLAB

#define UART_LCR_DLAB (0x1U << 7)

Divisor Latch Access Bit

## ◆ UART_LCR_PARITY_EVEN

#define UART_LCR_PARITY_EVEN (0x3U << 3)

Even parity (Sets the parity bit so that the count of bits set is an even number)

## ◆ UART_LCR_PARITY_MARK

#define UART_LCR_PARITY_MARK (0x5U << 3)

Mark parity (Leaves the parity bit set to 1)

## ◆ UART_LCR_PARITY_Msk

#define UART_LCR_PARITY_Msk (0x7U << 3)

Parity field mask bit

## ◆ UART_LCR_PARITY_NONE

#define UART_LCR_PARITY_NONE (0x0U << 3)

No parity

## ◆ UART_LCR_PARITY_ODD

#define UART_LCR_PARITY_ODD (0x1U << 3)

Odd parity (Sets the parity bit so that the count of bits set is an odd number)

## ◆ UART_LCR_PARITY_SPACE

#define UART_LCR_PARITY_SPACE (0x7U << 3)

Space parity (Leaves the parity bit set to 0)

## ◆ UART_LCR_SBS_1BIT

#define UART_LCR_SBS_1BIT (0x0U << 2)

1 stop bit

## ◆ UART_LCR_SBS_2BIT

#define UART_LCR_SBS_2BIT (0x1U << 2)

2 stop bits (1.5 stop bits when data length is 5 bits)

## ◆ UART_LCR_SBS_Msk

#define UART_LCR_SBS_Msk (0x1U << 2)

Stop bit select field mask bit

## ◆ UART_LCR_WLS_5BIT

#define UART_LCR_WLS_5BIT (0x0U << 0)

Word lenghth is 5 bits

## ◆ UART_LCR_WLS_6BIT

#define UART_LCR_WLS_6BIT (0x1U << 0)

Word lenghth is 6 bits

## ◆ UART_LCR_WLS_7BIT

#define UART_LCR_WLS_7BIT (0x2U << 0)

Word lenghth is 7 bits

## ◆ UART_LCR_WLS_8BIT

#define UART_LCR_WLS_8BIT (0x3U << 0)

Word lenghth is 8 bits

## ◆ UART_LCR_WLS_Msk

#define UART_LCR_WLS_Msk (0x3U << 0)

Word lenghth field mask bit

## ◆ UART_LSR_ADDR_RCVD

#define UART_LSR_ADDR_RCVD (0x1U << 8)

Address Received bit

## ◆ UART_LSR_BI

#define UART_LSR_BI (0x1U << 4)

Break Interrupt bit

## ◆ UART_LSR_DR

#define UART_LSR_DR (0x1U << 0)

Data Ready bit

## ◆ UART_LSR_FE

#define UART_LSR_FE (0x1U << 3)

Framing error bit

## ◆ UART_LSR_OE

#define UART_LSR_OE (0x1U << 1)

Overrun error bit

## ◆ UART_LSR_PE

#define UART_LSR_PE (0x1U << 2)

Parity error bit

## ◆ UART_LSR_RFE

#define UART_LSR_RFE (0x1U << 7)

Receiver FIFO Error bit

## ◆ UART_LSR_TEMT

#define UART_LSR_TEMT (0x1U << 6)

Transmitter Empty bit

## ◆ UART_LSR_THRE

#define UART_LSR_THRE (0x1U << 5)

Transmit Holding Register Empty bit

## ◆ UART_MCR_AFCE

#define UART_MCR_AFCE (0x1U << 5)

Auto Flow Control Enable

## ◆ UART_MCR_LB

#define UART_MCR_LB (0x1U << 4)

LoopBack Bit

## ◆ UART_MCR_RTS

#define UART_MCR_RTS (0x1U << 1)

Request to Send

## ◆ UART_MCR_SIRE

#define UART_MCR_SIRE (0x1U << 6)

SIR Mode Enable

## ◆ UART_MSR_CTS

#define UART_MSR_CTS (0x1U << 4)

Clear to Send

## ◆ UART_MSR_DCTS

#define UART_MSR_DCTS (0x1U << 0)

Delta Clear to Send

## ◆ UART_SBCR_SBCB

#define UART_SBCR_SBCB (0x1U << 0)

Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]).

## ◆ UART_SDMAM_SDMAM

#define UART_SDMAM_SDMAM (0x1U << 0)

Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]).

## ◆ UART_SFE_SFE

#define UART_SFE_SFE (0x1U << 0)

Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]).

## ◆ UART_SRR_RFR

#define UART_SRR_RFR (0x1U << 1)

RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]).

## ◆ UART_SRR_UR

#define UART_SRR_UR (0x1U << 0)

UART Reset

## ◆ UART_SRR_XFR

#define UART_SRR_XFR (0x1U << 2)

XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]).

## ◆ UART_SRT_LEV0

#define UART_SRT_LEV0 (0x0U)

1 character in the FIFO

## ◆ UART_SRT_LEV1

#define UART_SRT_LEV1 (0x1U)

FIFO 1/4 full

## ◆ UART_SRT_LEV2

#define UART_SRT_LEV2 (0x2U)

FIFO 1/2 full

## ◆ UART_SRT_LEV3

#define UART_SRT_LEV3 (0x3U)

FIFO 2 less than full

## ◆ UART_SRTS_SRTS

#define UART_SRTS_SRTS (0x1U << 0)

Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]).

## ◆ UART_STET_LEV0

#define UART_STET_LEV0 (0x0U)

FIFO empty

## ◆ UART_STET_LEV1

#define UART_STET_LEV1 (0x1U)

2 characters in the FIFO

## ◆ UART_STET_LEV2

#define UART_STET_LEV2 (0x2U)

FIFO 1/4 full

## ◆ UART_STET_LEV3

#define UART_STET_LEV3 (0x3U)

FIFO 1/2 full

## ◆ UART_USR_BUSY

#define UART_USR_BUSY (0x1U << 0)

UART Busy

## ◆ UART_USR_RFF

#define UART_USR_RFF (0x1U << 4)

Receive FIFO Full

## ◆ UART_USR_RFNE

#define UART_USR_RFNE (0x1U << 3)

Receive FIFO Not Empty

## ◆ UART_USR_TFE

#define UART_USR_TFE (0x1U << 2)

Transmit FIFO Empty

## ◆ UART_USR_TFNF

#define UART_USR_TFNF (0x1U << 1)

Transmit FIFO Not Full

## ◆ USB_CSR0_DATAEND

#define USB_CSR0_DATAEND (0x1U << 3)

No description

## ◆ USB_CSR0_INPKTRDY

#define USB_CSR0_INPKTRDY (0x1U << 1)

No description

## ◆ USB_CSR0_OUTPKTRDY

#define USB_CSR0_OUTPKTRDY (0x1U << 0)

No description

## ◆ USB_CSR0_SENDSTALL

#define USB_CSR0_SENDSTALL (0x1U << 5)

No description

## ◆ USB_CSR0_SENTSTALL

#define USB_CSR0_SENTSTALL (0x1U << 2)

No description

## ◆ USB_CSR0_SETUPEND

#define USB_CSR0_SETUPEND (0x1U << 4)

No description

## ◆ USB_CSR0_SVDOUTPKTRDY

#define USB_CSR0_SVDOUTPKTRDY (0x1U << 6)

No description

## ◆ USB_CSR0_SVDSETUPEND

#define USB_CSR0_SVDSETUPEND (0x1U << 7)

No description

## ◆ USB_FADDR_FADDR_Msk

#define USB_FADDR_FADDR_Msk (0x7FU)

The function address field mask

## ◆ USB_FADDR_UPDATE

#define USB_FADDR_UPDATE (0x1U << 7)

Set when FAddr is written

## ◆ USB_INCSR1_CLRDATATOG

#define USB_INCSR1_CLRDATATOG (0x1U << 6)

No description

## ◆ USB_INCSR1_FIFONE

#define USB_INCSR1_FIFONE (0x1U << 1)

No description

## ◆ USB_INCSR1_FLUSHFIFO

#define USB_INCSR1_FLUSHFIFO (0x1U << 3)

No description

## ◆ USB_INCSR1_INPKTRDY

#define USB_INCSR1_INPKTRDY (0x1U << 0)

No description

## ◆ USB_INCSR1_SENDSTALL

#define USB_INCSR1_SENDSTALL (0x1U << 4)

No description

## ◆ USB_INCSR1_SENTSTALL

#define USB_INCSR1_SENTSTALL (0x1U << 5)

No description

## ◆ USB_INCSR1_UNDERRUN

#define USB_INCSR1_UNDERRUN (0x1U << 2)

No description

## ◆ USB_INCSR2_AUTOSET

#define USB_INCSR2_AUTOSET (0x1U << 7)

No description

## ◆ USB_INCSR2_DIRSEL

#define USB_INCSR2_DIRSEL (0x1U << 5)

No description

## ◆ USB_INCSR2_DMAEN

#define USB_INCSR2_DMAEN (0x1U << 4)

No description

## ◆ USB_INCSR2_FRCDATATOG

#define USB_INCSR2_FRCDATATOG (0x1U << 3)

No description

## ◆ USB_INCSR2_ISO

#define USB_INCSR2_ISO (0x1U << 6)

No description

## ◆ USB_INTRIN_EP0

#define USB_INTRIN_EP0 (0x1U << 0)

No description

## ◆ USB_INTRIN_IN1

#define USB_INTRIN_IN1 (0x1U << 1)

No description

## ◆ USB_INTRIN_IN2

#define USB_INTRIN_IN2 (0x1U << 2)

No description

## ◆ USB_INTRIN_IN3

#define USB_INTRIN_IN3 (0x1U << 3)

No description

## ◆ USB_INTRINE_EP0E

#define USB_INTRINE_EP0E (0x1U << 0)

No description

## ◆ USB_INTRINE_IN1E

#define USB_INTRINE_IN1E (0x1U << 1)

No description

## ◆ USB_INTRINE_IN2E

#define USB_INTRINE_IN2E (0x1U << 2)

No description

## ◆ USB_INTRINE_IN3E

#define USB_INTRINE_IN3E (0x1U << 3)

No description

## ◆ USB_INTROUT_OUT1

#define USB_INTROUT_OUT1 (0x1U << 1)

No description

## ◆ USB_INTROUT_OUT2

#define USB_INTROUT_OUT2 (0x1U << 2)

No description

## ◆ USB_INTROUT_OUT3

#define USB_INTROUT_OUT3 (0x1U << 3)

No description

## ◆ USB_INTROUTE_OUT1E

#define USB_INTROUTE_OUT1E (0x1U << 1)

No description

## ◆ USB_INTROUTE_OUT2E

#define USB_INTROUTE_OUT2E (0x1U << 2)

No description

## ◆ USB_INTROUTE_OUT3E

#define USB_INTROUTE_OUT3E (0x1U << 3)

No description

## ◆ USB_INTRUSB_RSTIS

#define USB_INTRUSB_RSTIS (0x1U << 2)

No description

## ◆ USB_INTRUSB_RSUIS

#define USB_INTRUSB_RSUIS (0x1U << 1)

No description

## ◆ USB_INTRUSB_SOFIS

#define USB_INTRUSB_SOFIS (0x1U << 3)

No description

## ◆ USB_INTRUSB_SUSIS

#define USB_INTRUSB_SUSIS (0x1U << 0)

No description

## ◆ USB_INTRUSBE_RSTIE

#define USB_INTRUSBE_RSTIE (0x1U << 2)

No description

## ◆ USB_INTRUSBE_RSUIE

#define USB_INTRUSBE_RSUIE (0x1U << 1)

No description

## ◆ USB_INTRUSBE_SOFIE

#define USB_INTRUSBE_SOFIE (0x1U << 3)

No description

## ◆ USB_INTRUSBE_SUSIE

#define USB_INTRUSBE_SUSIE (0x1U << 0)

No description

## ◆ USB_OUTCSR1_CLRDATATOG

#define USB_OUTCSR1_CLRDATATOG (0x1U << 7)

No description

## ◆ USB_OUTCSR1_DATAERROR

#define USB_OUTCSR1_DATAERROR (0x1U << 3)

No description

## ◆ USB_OUTCSR1_FIFOFULL

#define USB_OUTCSR1_FIFOFULL (0x1U << 1)

No description

## ◆ USB_OUTCSR1_FLUSHFIFO

#define USB_OUTCSR1_FLUSHFIFO (0x1U << 4)

No description

## ◆ USB_OUTCSR1_OUTPKTRDY

#define USB_OUTCSR1_OUTPKTRDY (0x1U << 0)

No description

## ◆ USB_OUTCSR1_OVERRUN

#define USB_OUTCSR1_OVERRUN (0x1U << 2)

No description

## ◆ USB_OUTCSR1_SENDSTALL

#define USB_OUTCSR1_SENDSTALL (0x1U << 5)

No description

## ◆ USB_OUTCSR1_SENTSTALL

#define USB_OUTCSR1_SENTSTALL (0x1U << 6)

No description

## ◆ USB_OUTCSR2_AUTOCLR

#define USB_OUTCSR2_AUTOCLR (0x1U << 7)

No description

## ◆ USB_OUTCSR2_DMAEN

#define USB_OUTCSR2_DMAEN (0x1U << 5)

No description

## ◆ USB_OUTCSR2_DMAMODE

#define USB_OUTCSR2_DMAMODE (0x1U << 4)

No description

## ◆ USB_OUTCSR2_ISO

#define USB_OUTCSR2_ISO (0x1U << 6)

No description

## ◆ USB_POWER_ISOUD

#define USB_POWER_ISOUD (0x1U << 7)

No description

## ◆ USB_POWER_RESUME

#define USB_POWER_RESUME (0x1U << 2)

No description

## ◆ USB_POWER_SUSEN

#define USB_POWER_SUSEN (0x1U << 0)

No description

## ◆ USB_POWER_SUSMD

#define USB_POWER_SUSMD (0x1U << 1)

No description

## ◆ USB_POWER_USBRST

#define USB_POWER_USBRST (0x1U << 3)

No description

## ◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI ((uint16_t)0x0200)

Early Wakeup Interrupt

## ◆ WWDG_CFR_W

#define WWDG_CFR_W ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

## ◆ WWDG_CFR_W0

#define WWDG_CFR_W0 ((uint16_t)0x0001)

Bit 0

## ◆ WWDG_CFR_W1

#define WWDG_CFR_W1 ((uint16_t)0x0002)

Bit 1

## ◆ WWDG_CFR_W2

#define WWDG_CFR_W2 ((uint16_t)0x0004)

Bit 2

## ◆ WWDG_CFR_W3

#define WWDG_CFR_W3 ((uint16_t)0x0008)

Bit 3

## ◆ WWDG_CFR_W4

#define WWDG_CFR_W4 ((uint16_t)0x0010)

Bit 4

## ◆ WWDG_CFR_W5

#define WWDG_CFR_W5 ((uint16_t)0x0020)

Bit 5

## ◆ WWDG_CFR_W6

#define WWDG_CFR_W6 ((uint16_t)0x0040)

Bit 6

## ◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

## ◆ WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)

Bit 0

## ◆ WWDG_CFR_WDGTB1

#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)

Bit 1

## ◆ WWDG_CR_T

#define WWDG_CR_T ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

## ◆ WWDG_CR_T0

#define WWDG_CR_T0 ((uint8_t)0x01)

Bit 0

## ◆ WWDG_CR_T1

#define WWDG_CR_T1 ((uint8_t)0x02)

Bit 1

## ◆ WWDG_CR_T2

#define WWDG_CR_T2 ((uint8_t)0x04)

Bit 2

## ◆ WWDG_CR_T3

#define WWDG_CR_T3 ((uint8_t)0x08)

Bit 3

## ◆ WWDG_CR_T4

#define WWDG_CR_T4 ((uint8_t)0x10)

Bit 4

## ◆ WWDG_CR_T5

#define WWDG_CR_T5 ((uint8_t)0x20)

Bit 5

## ◆ WWDG_CR_T6

#define WWDG_CR_T6 ((uint8_t)0x40)

Bit 6

## ◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA ((uint8_t)0x80)

Activation bit

## ◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF ((uint8_t)0x01)

Early Wakeup Interrupt Flag