成员变量
uint32_t	RESERVED0 [7]

__IOM uint32_t	BGCR2

uint32_t	RESERVED1 [3]

__IOM uint32_t	MHSIENR

__IOM uint32_t	MHSISR

uint32_t	RESERVED2

__IOM uint32_t	FHSIENR

__IOM uint32_t	FHSISR

uint32_t	RESERVED3

__IOM uint32_t	LSIENR

__IOM uint32_t	LSISR

__IOM uint32_t	HSECR0

__IOM uint32_t	HSECR1

uint32_t	RESERVED4

__IOM uint32_t	HSESR

uint32_t	RESERVED5 [6]

__IOM uint32_t	PLLCR

__IOM uint32_t	PLLENR

__IOM uint32_t	PLLSR

__IOM uint32_t	PVDCR

__IOM uint32_t	PVDENR

uint32_t	RESERVED6

__IOM uint32_t	SARENR

__IOM uint32_t	USBPCR

__IOM uint32_t	PORCR

__IOM uint32_t	CMPACR

__IOM uint32_t	CMPBCR

__IOM uint32_t	ISR

__IOM uint32_t	IER

__IOM uint32_t	ICR

__IOM uint32_t	CMPASR

__IOM uint32_t	CMPBSR

__IOM uint32_t	DCSSENR

__IOM uint32_t	DCSSCR

结构体成员变量说明

◆ BGCR2

__IOM uint32_t BGCR2

BandGap control register 2, Address offset: 0x01C

◆ CMPACR

__IOM uint32_t CMPACR

CMPA control register, Address offset: 0x098

◆ CMPASR

__IOM uint32_t CMPASR

CMPA status register, Address offset: 0x0AC

◆ CMPBCR

__IOM uint32_t CMPBCR

CMPB control register, Address offset: 0x09C

◆ CMPBSR

__IOM uint32_t CMPBSR

CMPB status register, Address offset: 0x0B0

◆ DCSSCR

__IOM uint32_t DCSSCR

DCSS control register, Address offset: 0x0B8

◆ DCSSENR

__IOM uint32_t DCSSENR

DCSS enable register, Address offset: 0x0B4

◆ FHSIENR

__IOM uint32_t FHSIENR

FHSI enable register, Address offset: 0x038

◆ FHSISR

__IOM uint32_t FHSISR

FHSI status register, Address offset: 0x03C

◆ HSECR0

__IOM uint32_t HSECR0

HSE control register 0, Address offset: 0x04C

◆ HSECR1

__IOM uint32_t HSECR1

HSE control register 1, Address offset: 0x050

◆ HSESR

__IOM uint32_t HSESR

HSE status register, Address offset: 0x058

◆ ICR

__IOM uint32_t ICR

Interrupt clear register, Address offset: 0x0A8

◆ IER

__IOM uint32_t IER

Interrupt enable register, Address offset: 0x0A4

◆ ISR

__IOM uint32_t ISR

Interrupt status register, Address offset: 0x0A0

◆ LSIENR

__IOM uint32_t LSIENR

LSI enable register, Address offset: 0x044

◆ LSISR

__IOM uint32_t LSISR

LSI status register, Address offset: 0x048

◆ MHSIENR

__IOM uint32_t MHSIENR

MHSI enable register, Address offset: 0x02C

◆ MHSISR

__IOM uint32_t MHSISR

MHSI status register, Address offset: 0x030

◆ PLLCR

__IOM uint32_t PLLCR

PLL control register, Address offset: 0x074

◆ PLLENR

__IOM uint32_t PLLENR

PLl enable register, Address offset: 0x078

◆ PLLSR

__IOM uint32_t PLLSR

PLL status register, Address offset: 0x07C

◆ PORCR

__IOM uint32_t PORCR

POR control register, Address offset: 0x094

◆ PVDCR

__IOM uint32_t PVDCR

PVD control register, Address offset: 0x080

◆ PVDENR

__IOM uint32_t PVDENR

PVD enable register, Address offset: 0x084

◆ RESERVED0

uint32_t RESERVED0[7]

Reserved, 0x000 - 0x018

◆ RESERVED1

uint32_t RESERVED1[3]

Reserved, 0x020 - 0x028

◆ RESERVED2

uint32_t RESERVED2

Reserved, 0x034

◆ RESERVED3

uint32_t RESERVED3

Reserved, 0x040

◆ RESERVED4

uint32_t RESERVED4

Reserved, 0x054

◆ RESERVED5

uint32_t RESERVED5[6]

Reserved, 0x05C - 0x070

◆ RESERVED6

uint32_t RESERVED6

Reserved, 0x088

◆ SARENR

__IOM uint32_t SARENR

SAR ADC enable register, Address offset: 0x08C

◆ USBPCR

__IOM uint32_t USBPCR

USB PHY control register, Address offset: 0x090

该结构体的文档由以下文件生成:

mg32f10x.h