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MG32F10x Standard Peripherals Firmware Library
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成员变量 | |
| __IOM uint32_t | RTCCR |
| __IOM uint32_t | CR |
| __IOM uint32_t | CSR |
| uint32_t | RESERVED0 |
| __IOM uint32_t | DR1 |
| __IOM uint32_t | DR2 |
| __IOM uint32_t | DR3 |
| __IOM uint32_t | DR4 |
| __IOM uint32_t | DR5 |
| __IOM uint32_t | DR6 |
| __IOM uint32_t | DR7 |
| __IOM uint32_t | DR8 |
| __IOM uint32_t | DR9 |
| __IOM uint32_t | DR10 |
| __IOM uint32_t | DR11 |
| __IOM uint32_t | DR12 |
| __IOM uint32_t | DR13 |
| __IOM uint32_t | DR14 |
| __IOM uint32_t | DR15 |
| __IOM uint32_t | DR16 |
| __IOM uint32_t | DR17 |
| __IOM uint32_t | DR18 |
| __IOM uint32_t | DR19 |
| __IOM uint32_t | DR20 |
| __IOM uint32_t | DR21 |
| uint32_t | RESERVED1 [39] |
| __IOM uint32_t | BDCR |
| __IOM uint32_t BDCR |
Backup domain control register, Address offset: 0x100
| __IOM uint32_t CR |
Backup control register, Address offset: 0x004
| __IOM uint32_t CSR |
Backup control/status register, Address offset: 0x008
| __IOM uint32_t DR1 |
Backup data register 1, Address offset: 0x010
| __IOM uint32_t DR10 |
Backup data register 10, Address offset: 0x034
| __IOM uint32_t DR11 |
Backup data register 11, Address offset: 0x038
| __IOM uint32_t DR12 |
Backup data register 12, Address offset: 0x03C
| __IOM uint32_t DR13 |
Backup data register 13, Address offset: 0x040
| __IOM uint32_t DR14 |
Backup data register 14, Address offset: 0x044
| __IOM uint32_t DR15 |
Backup data register 15, Address offset: 0x048
| __IOM uint32_t DR16 |
Backup data register 16, Address offset: 0x04C
| __IOM uint32_t DR17 |
Backup data register 17, Address offset: 0x050
| __IOM uint32_t DR18 |
Backup data register 18, Address offset: 0x054
| __IOM uint32_t DR19 |
Backup data register 19, Address offset: 0x058
| __IOM uint32_t DR2 |
Backup data register 2, Address offset: 0x014
| __IOM uint32_t DR20 |
Backup data register 20, Address offset: 0x05C
| __IOM uint32_t DR21 |
Backup data register 21, Address offset: 0x060
| __IOM uint32_t DR3 |
Backup data register 3, Address offset: 0x018
| __IOM uint32_t DR4 |
Backup data register 4, Address offset: 0x01C
| __IOM uint32_t DR5 |
Backup data register 5, Address offset: 0x020
| __IOM uint32_t DR6 |
Backup data register 6, Address offset: 0x024
| __IOM uint32_t DR7 |
Backup data register 7, Address offset: 0x028
| __IOM uint32_t DR8 |
Backup data register 8, Address offset: 0x02C
| __IOM uint32_t DR9 |
Backup data register 9, Address offset: 0x030
| uint32_t RESERVED0 |
Reserved, 0x00C
| uint32_t RESERVED1[39] |
Reserved, 0x064 - 0x0FC
| __IOM uint32_t RTCCR |
RTC clock calibration register, Address offset: 0x000