成员变量
__IOM uint32_t	PLLPRE

__IOM uint32_t	PLLSRC

__IOM uint32_t	MAINCLKSRC

__IOM uint32_t	MAINCLKUEN

uint32_t	RESERVED0

__IOM uint32_t	USBPRE

__IOM uint32_t	AHBPRE

__IOM uint32_t	APB1PRE

__IOM uint32_t	APB2PRE

__IOM uint32_t	MCLKPRE

__IOM uint32_t	I2SPRE

__IOM uint32_t	MCLKSRC

uint32_t	RESERVED1

__IOM uint32_t	USBFIFOCLKSRC

__IOM uint32_t	MCOSEL

__IOM uint32_t	AHBENR0

__IOM uint32_t	AHBENR1

__IOM uint32_t	AHBENR2

__IOM uint32_t	APB1ENR

__IOM uint32_t	APB2ENR

uint32_t	RESERVED2 [3]

__IOM uint32_t	RNGCLKENR

__IOM uint32_t	PCLKENR

__IOM uint32_t	IWDGCLKENR

uint32_t	RESERVED4

__IOM uint32_t	USBCLKENR

__IOM uint32_t	I2SCLKENR

__IOM uint32_t	SPIS1CLKENR

__IOM uint32_t	SPIS2CLKENR

__IOM uint32_t	USBFIFOCLKENR

uint32_t	RESERVED5 [2]

__IOM uint32_t	AHBRSTR1

uint32_t	RESERVED6

__IOM uint32_t	APB1RSTR

__IOM uint32_t	APB2RSTR

uint32_t	RESERVED7 [8]

__IOM uint32_t	I2SCLKRSTR

uint32_t	RESERVED8 [3]

__IOM uint32_t	CLRRSTSTAT

uint32_t	RESERVED9 [2]

__IOM uint32_t	BDRSTR

__IOM uint32_t	LSI2RTCENR

__IOM uint32_t	HSE2RTCENR

uint32_t	RESERVED10 [8]

__IOM uint32_t	RSTSTAT

结构体成员变量说明

◆ AHBENR0

__IOM uint32_t AHBENR0

RCC AHB peripheral clock enable register 0, Address offset: 0x03C

◆ AHBENR1

__IOM uint32_t AHBENR1

RCC AHB peripheral clock enable register 1, Address offset: 0x040

◆ AHBENR2

__IOM uint32_t AHBENR2

RCC AHB peripheral clock enable register 2, Address offset: 0x044

◆ AHBPRE

__IOM uint32_t AHBPRE

RCC AHB prescaler register, Address offset: 0x018

◆ AHBRSTR1

__IOM uint32_t AHBRSTR1

RCC AHB peripheral reset register 1, Address offset: 0x088

◆ APB1ENR

__IOM uint32_t APB1ENR

RCC APB1 peripheral clock enable register, Address offset: 0x048

◆ APB1PRE

__IOM uint32_t APB1PRE

RCC APB1 prescaler register, Address offset: 0x01C

◆ APB1RSTR

__IOM uint32_t APB1RSTR

RCC APB1 peripheral reset register, Address offset: 0x090

◆ APB2ENR

__IOM uint32_t APB2ENR

RCC APB2 peripheral clock enable register, Address offset: 0x04C

◆ APB2PRE

__IOM uint32_t APB2PRE

RCC APB2 prescaler register, Address offset: 0x020

◆ APB2RSTR

__IOM uint32_t APB2RSTR

RCC APB2 peripheral reset register, Address offset: 0x094

◆ BDRSTR

__IOM uint32_t BDRSTR

RCC Batt domain reset register, Address offset: 0x0D4

◆ CLRRSTSTAT

__IOM uint32_t CLRRSTSTAT

RCC clear reset status register, Address offset: 0x0C8

◆ HSE2RTCENR

__IOM uint32_t HSE2RTCENR

RCC HSE to RTC clock enable register, Address offset: 0x0DC

◆ I2SCLKENR

__IOM uint32_t I2SCLKENR

RCC I2S SCLK enable register, Address offset: 0x070

◆ I2SCLKRSTR

__IOM uint32_t I2SCLKRSTR

RCC I2S SCLK reset register, Address offset: 0x0B8

◆ I2SPRE

__IOM uint32_t I2SPRE

RCC I2S prescaler register, Address offset: 0x028

◆ IWDGCLKENR

__IOM uint32_t IWDGCLKENR

RCC IWDG clock enable register, Address offset: 0x064

◆ LSI2RTCENR

__IOM uint32_t LSI2RTCENR

RCC LSI to RTC clock enable register, Address offset: 0x0D8

◆ MAINCLKSRC

__IOM uint32_t MAINCLKSRC

RCC main clock source register, Address offset: 0x008

◆ MAINCLKUEN

__IOM uint32_t MAINCLKUEN

RCC main clock update enable register, Address offset: 0x00C

◆ MCLKPRE

__IOM uint32_t MCLKPRE

RCC MCLK prescaler register, Address offset: 0x024

◆ MCLKSRC

__IOM uint32_t MCLKSRC

RCC MCLK source register, Address offset: 0x02C

◆ MCOSEL

__IOM uint32_t MCOSEL

RCC MCO select register, Address offset: 0x038

◆ PCLKENR

__IOM uint32_t PCLKENR

RCC panel PCLK clock enable register, Address offset: 0x060

◆ PLLPRE

__IOM uint32_t PLLPRE

RCC PLL prescaler register, Address offset: 0x000

◆ PLLSRC

__IOM uint32_t PLLSRC

RCC PLL source register, Address offset: 0x004

◆ RESERVED0

uint32_t RESERVED0

Reserved, 0x010

◆ RESERVED1

uint32_t RESERVED1

Reserved, 0x030

◆ RESERVED10

uint32_t RESERVED10[8]

Reserved, 0x0E0 - 0x0FC

◆ RESERVED2

uint32_t RESERVED2[3]

Reserved, 0x050 - 0x058

◆ RESERVED4

uint32_t RESERVED4

Reserved, 0x068

◆ RESERVED5

uint32_t RESERVED5[2]

Reserved, 0x080 - 0x084

◆ RESERVED6

uint32_t RESERVED6

Reserved, 0x08C

◆ RESERVED7

uint32_t RESERVED7[8]

Reserved, 0x098 - 0x0B4

◆ RESERVED8

uint32_t RESERVED8[3]

Reserved, 0x0BC - 0x0C4

◆ RESERVED9

uint32_t RESERVED9[2]

Reserved, 0x0CC - 0x0D0

◆ RNGCLKENR

__IOM uint32_t RNGCLKENR

RCC RNG clock enable register, Address offset: 0x05C

◆ RSTSTAT

__IOM uint32_t RSTSTAT

RCC reset status register, Address offset: 0x100

◆ SPIS1CLKENR

__IOM uint32_t SPIS1CLKENR

RCC SPIS1 clock enable register, Address offset: 0x074

◆ SPIS2CLKENR

__IOM uint32_t SPIS2CLKENR

RCC SPIS2 clock enable register, Address offset: 0x078

◆ USBCLKENR

__IOM uint32_t USBCLKENR

RCC USB clock enable register, Address offset: 0x06C

◆ USBFIFOCLKENR

__IOM uint32_t USBFIFOCLKENR

RCC USB FIFO clock enable register, Address offset: 0x07C

◆ USBFIFOCLKSRC

__IOM uint32_t USBFIFOCLKSRC

RCC USB FIFO clock source register, Address offset: 0x034

◆ USBPRE

__IOM uint32_t USBPRE

RCC USB prescaler register, Address offset: 0x014

该结构体的文档由以下文件生成:

mg32f10x.h