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MG32F10x Standard Peripherals Firmware Library
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成员变量 | |
| __IM uint32_t | ID |
| __IM uint32_t | MEMSZ |
| uint32_t | RESERVED0 |
| __IM uint32_t | BTCR |
| __IM uint32_t | MEMWEN |
| __IM uint32_t | SENDEV |
| __IM uint32_t | RSTCR |
| __IM uint32_t | IF4LCK |
| __IM uint32_t | IF5LCK |
| __IM uint32_t | IF6LCK |
| __IM uint32_t | IF7LCK |
| uint32_t | RESERVED1 [2] |
| __IM uint32_t | BTSR |
| __IM uint32_t BTCR |
SYS BOOT Control register, Address offset: 0x00C
| __IM uint32_t BTSR |
SYS Boot Status register, Address offset: 0x034
| __IM uint32_t ID |
SYS ID register, Address offset: 0x000
| __IM uint32_t IF4LCK |
SYS Info4 Write Enable register, Address offset: 0x01C
| __IM uint32_t IF5LCK |
SYS Info5 Write Enable register, Address offset: 0x020
| __IM uint32_t IF6LCK |
SYS Info6 Write Enable register, Address offset: 0x024
| __IM uint32_t IF7LCK |
SYS Info7 Write Enable register, Address offset: 0x028
| __IM uint32_t MEMSZ |
SYS Memory Size register, Address offset: 0x004
| __IM uint32_t MEMWEN |
SYS Main Memory Write Enable register, Address offset: 0x010
| uint32_t RESERVED0 |
Reserved, 0x008
| uint32_t RESERVED1[2] |
Reserved, 0x02C - 0x030
| __IM uint32_t RSTCR |
SYS Reset Control register, Address offset: 0x018
| __IM uint32_t SENDEV |
SYS Second Development Control register, Address offset: 0x014