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MG32F10x Standard Peripherals Firmware Library
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成员变量 | |
| union { | |
| __IM uint32_t RBR | |
| __OM uint32_t THR | |
| __IOM uint32_t DLL | |
| }; | |
| union { | |
| __IOM uint32_t DLH | |
| __IOM uint32_t IER | |
| }; | |
| union { | |
| __IM uint32_t IIR | |
| __OM uint32_t FCR | |
| }; | |
| __IOM uint32_t | LCR |
| __IOM uint32_t | MCR |
| __IM uint32_t | LSR |
| __IM uint32_t | MSR |
| __IOM uint32_t | SCR |
| uint32_t | RESERVED0 [23] |
| __IM uint32_t | USR |
| __IM uint32_t | TFL |
| __IM uint32_t | RFL |
| __OM uint32_t | SRR |
| __IOM uint32_t | SRTS |
| __IOM uint32_t | SBCR |
| uint32_t | RESERVED1 |
| __IOM uint32_t | SFE |
| __IOM uint32_t | SRT |
| __IOM uint32_t | STET |
| __IOM uint32_t | HTX |
| __OM uint32_t | DMASA |
| uint32_t | RESERVED2 [5] |
| __IOM uint32_t | DLF |
| __IOM uint32_t | RAR |
| __IOM uint32_t | TAR |
| __IOM uint32_t | EXTLCR |
| __IOM uint32_t DLF |
Divisor Latch Fractional Value, Address offset: 0x0C0
| __IOM uint32_t DLH |
Divisor Latch(High), Address offset: 0x004
| __IOM uint32_t DLL |
Divisor Latch(Low), Address offset: 0x000
| __OM uint32_t DMASA |
DMA Software Acknowledge, Address offset: 0x0A8
| __IOM uint32_t EXTLCR |
Line Extended Control Register, Address offset: 0x0CC
| __OM uint32_t FCR |
FIFO Control Register, Address offset: 0x008
| __IOM uint32_t HTX |
Halt TX, Address offset: 0x0A4
| __IOM uint32_t IER |
Interrupt Enable Register, Address offset: 0x004
| __IM uint32_t IIR |
Interrupt Identification Register, Address offset: 0x008
| __IOM uint32_t LCR |
Line Control Register, Address offset: 0x00C
| __IM uint32_t LSR |
Line Status Register, Address offset: 0x014
| __IOM uint32_t MCR |
Modem Control Register, Address offset: 0x010
| __IM uint32_t MSR |
Modem Status Register, Address offset: 0x018
| __IOM uint32_t RAR |
Receive Address Register, Address offset: 0x0C4
| __IM uint32_t RBR |
Receive Buffer Register, Address offset: 0x000
| uint32_t RESERVED0[23] |
Reserved, 0x020 - 0x078
| uint32_t RESERVED1 |
Reserved, 0x094
| uint32_t RESERVED2[5] |
Reserved, 0x0AC - 0x0BC
| __IM uint32_t RFL |
Receive FIFO Level, Address offset: 0x084
| __IOM uint32_t SBCR |
Shadow Break Control Register, Address offset: 0x090
| __IOM uint32_t SCR |
Scratchpad Register, Address offset: 0x01C
| __IOM uint32_t SFE |
Shadow FIFO Enable, Address offset: 0x098
| __OM uint32_t SRR |
Software Reset Register, Address offset: 0x088
| __IOM uint32_t SRT |
Shadow RCVR Trigger, Address offset: 0x09C
| __IOM uint32_t SRTS |
Shadow Request to Send, Address offset: 0x08C
| __IOM uint32_t STET |
Shadow TX Empty Trigger, Address offset: 0x0A0
| __IOM uint32_t TAR |
Transmit Address Register, Address offset: 0x0C8
| __IM uint32_t TFL |
Transmit FIFO Level, Address offset: 0x080
| __OM uint32_t THR |
Transmit Holding Register, Address offset: 0x000
| __IM uint32_t USR |
UART Status Register, Address offset: 0x07C