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MG32F10x Standard Peripherals Firmware Library
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成员变量 | |
| __IOM uint8_t | FADDR |
| __IOM uint8_t | POWER |
| __IM uint8_t | INTRIN |
| uint8_t | RESERVED0 |
| __IM uint8_t | INTROUT |
| uint8_t | RESERVED1 |
| __IM uint8_t | INTRUSB |
| __IOM uint8_t | INTRINE |
| uint8_t | RESERVED2 |
| __IOM uint8_t | INTROUTE |
| uint8_t | RESERVED3 |
| __IOM uint8_t | INTRUSBE |
| __IM uint8_t | FRAMEL |
| __IM uint8_t | FRAMEH |
| __IOM uint8_t | INDEX |
| uint8_t | RESERVED4 |
| __IOM uint8_t | INMAXP |
| union { | |
| __IOM uint8_t CSR0 | |
| __IOM uint8_t INCSR1 | |
| }; | |
| __IOM uint8_t | INCSR2 |
| __IOM uint8_t | OUTMAXP |
| __IOM uint8_t | OUTCSR1 |
| __IOM uint8_t | OUTCSR2 |
| union { | |
| __IM uint8_t COUNT0 | |
| __IM uint8_t OUTCOUNTL | |
| }; | |
| __IM uint8_t | OUTCOUNTH |
| uint8_t | RESERVED5 [8] |
| __IOM uint32_t | FIFO [16] |
| uint32_t | RESERVED6 [104] |
| __IOM uint32_t | DMAINTR |
| struct { | |
| __IOM uint32_t CNTL | |
| __IOM uint32_t ADDR | |
| __IOM uint32_t COUNT | |
| uint32_t RESERVED | |
| } | DMACH [8] |
| __IOM uint32_t ADDR |
DMA Address Register for DMA channel x, Address offset: 0x208, 0x218, 0x228
| __IOM uint32_t CNTL |
DMA Control Register for DMA channel x, Address offset: 0x204, 0x214, 0x224
| __IOM uint32_t COUNT |
DMA Count Register for DMA channel x, Address offset: 0x20C, 0x21C, 0x22C
| __IM uint8_t COUNT0 |
Number of received bytes in Endpoint 0 FIFO, Address offset: 0x016
| __IOM uint8_t CSR0 |
Control Status register for Endpoint 0, Address offset: 0x011
| __IOM uint32_t DMAINTR |
DMA Interrupt Register, Address offset: 0x200
| __IOM uint8_t FADDR |
Function address register, Address offset: 0x000
| __IOM uint32_t FIFO[16] |
FIFOs for Endpoints 0 to 15 (must accessed by bytes), Address offset: 0x020 - 0x05F
| __IM uint8_t FRAMEH |
Frame number bits 8 to 10, Address offset: 0x00D
| __IM uint8_t FRAMEL |
Frame number bits 0 to 7, Address offset: 0x00C
| __IOM uint8_t INCSR1 |
Control Status register 1 for IN endpoint, Address offset: 0x011
| __IOM uint8_t INCSR2 |
Control Status register 2 for IN endpoint, Address offset: 0x012
| __IOM uint8_t INDEX |
Index register, Address offset: 0x00E
| __IOM uint8_t INMAXP |
Maximum packet size for IN endpoint, Address offset: 0x010
| __IM uint8_t INTRIN |
Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3, Address offset: 0x002
| __IOM uint8_t INTRINE |
Interrupt enable register for IntrIn, Address offset: 0x007
| __IM uint8_t INTROUT |
Interrupt register for OUT Endpoints 1 to 3, Address offset: 0x004
| __IOM uint8_t INTROUTE |
Interrupt enable register for IntrOut, Address offset: 0x009
| __IM uint8_t INTRUSB |
Interrupt register for common USB interrupts, Address offset: 0x006
| __IOM uint8_t INTRUSBE |
Interrupt enable register for IntrUSB, Address offset: 0x00B
| __IM uint8_t OUTCOUNTH |
Number of bytes in OUT endpoint FIFO (upper byte), Address offset: 0x017
| __IM uint8_t OUTCOUNTL |
Number of bytes in OUT endpoint FIFO (lower byte), Address offset: 0x016
| __IOM uint8_t OUTCSR1 |
Control Status register 1 for OUT endpoint, Address offset: 0x014
| __IOM uint8_t OUTCSR2 |
Control Status register 2 for OUT endpoint, Address offset: 0x015
| __IOM uint8_t OUTMAXP |
Maximum packet size for OUT endpoint, Address offset: 0x013
| __IOM uint8_t POWER |
Power management register, Address offset: 0x001
| uint8_t RESERVED0 |
Reserved, 0x003
| uint8_t RESERVED1 |
Reserved, 0x005
| uint8_t RESERVED2 |
Reserved, 0x008
| uint8_t RESERVED3 |
Reserved, 0x00A
| uint8_t RESERVED4 |
Reserved, 0x00F
| uint8_t RESERVED5[8] |
Reserved, 0x018 - 0x01F
| uint32_t RESERVED6[104] |
Reserved, 0x060 - 0x1FC