產品資訊

Features Document Support

80C51 Central Processing Unit
3V/5V operation voltage, built-in Low-Voltage Reset circuit.
Optional 12T or 6T mode
Max operation frequency up to 48MHz@12T or 24MHz@6T
63KB on-chip program memory
ISP capability; optional 1KB/2KB/4KB ISP memory shared with application flash memory.
On-chip 256 byte scratch-pad RAM and 1024 byte auxiliary RAM; Be capable of addressing up to 64K bytes external memory
MOVC-disabling, encrypting, and locking flash memory realize security mechanism.
Three 16-bit timer/counter, Timer2 is an up/down counter with programmable clock output on P1.0
Eight sources, four-level-priority interrupt capability
Enhanced UART, provides frame-error detection and hardware address-recognition
Dual DPTR for fast-accessing of data memory
15 bits Watch-Dog-Timer with 8-bit pre-scalar, one-time enabled
Power control: idle mode and power-down mode; Power-down can be woken-up by P3.2/P3.3/P4.3
Low EMI: inhibit ALE emission
Four 8-bit bi-directional ports; extra four-bit additional P4 are available for PLCC-44 and PQPF-44
On-Chip flash program/data memory:
- The data endurance of the embedded flash gets over 20,000 times.
- 21 years data retention is guaranteed.